HI5767/2CB - 10-Bit 20/40/60 MSPS ADC | Intersil | SOIC-28
Référence : HI5767/2CB ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $1.15 | $1,15 |
| 10 | $1.03 | $10,30 |
| 100 | $0.92 | $92,00 |
| 500 | $0.81 | $405,00 |
| 1 000 | $0.72 | $720,00 |
HI5767/2CB Présentation
An analog-to-digital converter (ADC) is a data-acquisition component that converts continuous-time analog signals into discrete digital codes at a fixed sample rate, enabling downstream digital signal processing. Within the broader signal-chain hierarchy, the HI5767/2CB sits between analog conditioning (amplifier / filter) and the digital processor (DSP / FPGA / MCU); it is an example of a successive-approximation-class and pipelined converter used in interface and mixed-signal subsystems. The part belongs to the Data Acquisition family of integrated circuits, in the sub-domain of high-speed ADC interface ICs.
Key features include 10-bit resolution, sample rates of 20/40/60 MSPS via speed-grade selection, CMOS process for low power dissipation (typical 150 mW at 40 MSPS), a 250 MHz analog input bandwidth, and an internal 2.5 V reference that may be overridden by an external reference for absolute accuracy. The architecture yields differential nonlinearity of ±0.4 LSB and integral nonlinearity of ±0.8 LSB.
The on-chip pipeline architecture interleaves sample-and-hold stages with low-resolution flash sub-ADCs and a digital error-correction block, achieving low-latency conversion suitable for single-shot or repetitive capture. The CMOS implementation gives the part low glitch energy and good aperture timing, important for undersampling applications. The analog input supports single-ended 0.5 Vp-p or 1.0 Vp-p full-scale ranges.
Typical applications for the HI5767/2CB include high-speed instrumentation, digital oscilloscopes, IF/baseband signal conversion in communications equipment, medical imaging front-ends, and CCD/CIS imaging pipelines. Cable equalization, radar baseband capture, and machine-vision frame-grabber front-ends also benefit from its 60 MSPS capability and integrated reference.
Designers should pay attention to input-common-mode and clock-dither performance: the analog input must see proper termination and a 50 ohm shunt, and the encode clock should be driven with low-jitter LVTTL/CMOS levels. Decoupling the analog and digital supplies independently is recommended to maintain spurious-free dynamic range.
This page synthesizes distributor pricing, drop-in-compatible ADC equivalents, and practical design notes that are not duplicated on the manufacturer datasheet page.
Alternatives de remplacement direct pour HI5767/2CB — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec HI5767/2CB (même facteur de forme et même empreinte) — différant par Architecture, Package, Resolution, Supply Voltage, Number of Channels.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
HI5766KCAZ
✅ Remplacement direct✓ En stock
$5.6 / unité
Voir la fiche technique →HI5714/7CB-T
✅ Remplacement direct✓ En stock
$9.2 / unité
Voir la fiche technique →HI5767/6CB
✅ Remplacement direct✓ En stock
$7.2 / unité
Voir la fiche technique →HI5767/2CBZ
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADS901E/1KG4
✅ Remplacement direct✓ En stock
$4.12 / unité
Voir la fiche technique →HI5767/2CB Valeurs maximales et caractéristiques électriques
| Manufacturer | Intersil (now part of Renesas Electronics) |
| Description | 10-Bit, 20/40/60 MSPS ADC with internal voltage reference |
| Résolution | 10 bits |
| Sample Rate | 20 / 40 / 60 MSPS (selected by speed grade) |
| Analog Input Bandwidth | 250 MHz (typical) |
| Number of Inputs | 1 single-ended analog input |
| Architecture | Pipelined with on-chip T/H |
| Internal Reference Voltage | 2.5 V (internal, overridable) |
| Power Dissipation | 150 mW typical at 40 MSPS |
| Tension d'alimentation | 5 V analog, 3.3 V-5 V digital (typical) |
| Output Interface | CMOS digital outputs (10-bit parallel) |
| Boîtier | 28-lead SOIC |
| Plage de température de fonctionnement | 0 °C to +70 °C (commercial) |
| Technology | CMOS monolithic |
| Speed Grade Suffix | /2CB = 40 MSPS grade |
Configuration des broches de HI5767/2CB
| Broche 1 | AIN — Analog input |
| Broche 2 | VREF — Internal reference bypass |
| Broche 3 | AGND — Analog ground |
| Broche 4 | AVDD — Analog supply (5 V) |
| Broche 5 | DGND — Digital ground |
| Broche 6 | DVDD — Digital supply (3.3-5 V) |
| Broche 7 | CLK — Encode clock input |
| Broche 8 | D9 (MSB) — Digital output bit 9 (MSB) |
| Broche 9 | D8 — Digital output bit 8 |
| Broche 10 | D7 — Digital output bit 7 |
| Broche 11 | D6 — Digital output bit 6 |
| Broche 12 | D5 — Digital output bit 5 |
| Broche 13 | D4 — Digital output bit 4 |
| Broche 14 | D3 — Digital output bit 3 |
| Broche 15 | D2 — Digital output bit 2 |
| Broche 16 | D1 — Digital output bit 1 |
| Broche 17 | D0 (LSB) — Digital output bit 0 (LSB) |
| Broche 18 | DRVDD — Output driver supply |
| Broche 19 | DRGND — Output driver ground |
| Broche 20 | FSR — Full-scale range select |
| Broche 21 | MODE — Mode/test pin |
| Broche 22 | NC — Not connected |
| Broche 23 | NC — Not connected |
| Broche 24 | NC — Not connected |
| Broche 25 | CMOUT — Common-mode output |
| Broche 26 | AGND — Analog ground |
| Broche 27 | REFGND — Reference ground |
| Broche 28 | AVDD — Analog supply (5 V) |
Applications typiques
HI5767/2CB convient pour 6 applications: High-Speed Data Acquisition Systems, Digital Oscilloscope Front-End, IF / Baseband Signal Conversion in Communications, Medical Imaging and Patient Monitoring, CCD/CIS Image Sensor Pipeline, Radar Baseband and Lidar Capture.
High-Speed Data Acquisition Systems
The HI5767/2CB's 40 MSPS sample rate and 10-bit resolution suit high-speed data-acquisition front-ends for laboratory instruments, vibration analyzers, and multi-channel transient recorders. The internal 2.5 V reference reduces BOM cost while the pipelined architecture delivers low-latency conversion needed for triggered single-shot capture. Compared with discrete T/H + flash ADC designs, the monolithic CMOS implementation saves 60 percent of board area and cuts power to ~150 mW typical at 40 MSPS. The 250 MHz analog input bandwidth also supports direct IF sampling, eliminating an external down-conversion mixer in many test systems.
Recommandé
Digital Oscilloscope Front-End
Digitizing 40 MHz-bandwidth analog inputs of entry-level oscilloscopes, the HI5767/2CB provides 10-bit vertical resolution with a 40 MSPS real-time sample rate that exceeds the 4x oversampling requirement for 10 MHz signals. The internal reference simplifies calibration across manufacturing lots, while the pipelined architecture supports segmented memory acquisition for capturing fast transient events. Power dissipation at ~150 mW enables fanless portable scope designs. The 28-SOIC footprint matches legacy oscilloscope analog board layouts that already accommodate Intersil's HI5767 family, allowing cost-effective through-hole-fabricator upgrades.
Recommandé
IF / Baseband Signal Conversion in Communications
In digital receivers, the HI5767/2CB digitizes IF signals directly thanks to its 250 MHz analog bandwidth, allowing designers to bypass a second mixer stage. A typical 21.4 MHz IF centered in the second Nyquist zone can be undersampled at 40 MSPS, achieving 10-bit dynamic range adequate for software-defined-radio baseband chains and cable-headend CMTS receivers. The CMOS pipeline yields low aperture jitter (~1 ps typical), preserving modulation integrity for QAM/PSK schemes, while the internal reference reduces BOM compared to external ADC drivers.
Recommandé
Medical Imaging and Patient Monitoring
Cost-sensitive medical imaging chains such as ultrasound baseband capture, endoscope CCD readout and patient-monitoring signal acquisition benefit from the HI5767/2CB's integrated reference and 40 MSPS throughput. The 10-bit dynamic range is sufficient for diagnostic-grade acquisition of physiological waveforms when paired with appropriate front-end gain. The 28-SOIC commercial-grade 0 to 70 °C window covers room-temperature clinical equipment, and the CMOS pipeline avoids high-voltage scaling that some medical-cert devices preclude. Validate IEC 60601 EMI margins with the bypass network shown in the datasheet.
Recommandé
CCD/CIS Image Sensor Pipeline
The HI5767/2CB digitizes analog outputs from CCD and CIS image sensors in document scanners, machine-vision cameras, and industrial inspection equipment. Its single-ended analog input accommodates the sensor's 0.5 V to 1.0 V pixel-rate output range, while the 40 MSPS throughput supports VGA-format frames at 30 Hz line-rate acquisition. Internal reference simplifies pixel-to-pixel calibration. Compared with discrete AD9826 + op-amp front-ends, this monolithic part reduces BOM by 30 percent and PCB area by 50 percent for compact camera modules.
Recommandé
Radar Baseband and Lidar Capture
Pulsed-radar baseband and lidar time-of-flight applications leverage the HI5767/2CB's 250 MHz analog bandwidth and 10-bit resolution to digitize intermediate-frequency return signals with sufficient dynamic range. The low-latency pipelined architecture preserves nanosecond timing accuracy needed for range-gating. Power dissipation of ~150 mW enables battery-operated portable radar modules. The 28-SOIC commercial temperature grade suits outdoor enclosures with internal heating, and the internal reference minimizes bias drift in automotive-grade security installations.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour HI5767/2CB — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | HI5766KCAZ | HI5714/7CB-T | HI5767/6CB | HI5767/2CBZ | ADS901E/1KG4 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics (legacy Intersil) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Texas Instruments |
| Package | 28-SOIC | 28-SOIC | 28-SOIC | 28-SOIC | 28-SOIC | 28-SOIC |
| Resolution | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits | 10 bits |
| Internal Reference | 2.5 V internal, overridable | Internal reference | Internal reference | 2.5 V internal, same die | 2.5 V internal, same die | External reference preferred |
| Lifecycle | Obsolete | Active (newer family member) | NRND | Obsolete | Obsolete | Active |
Principaux différenciateurs
- Internal 2.5 V reference removes external reference BOM (vs ADS901E/1KG4)
- Drop-in same-family upgrade to 60 MSPS without PCB change (vs HI5767/2CBZ)
- Pipeline architecture gives low conversion latency (vs HI5714/7CB-T)
- Wide 250 MHz analog input bandwidth supports IF sampling (vs ADS901E/1KG4)
Notes de conception
Supply the HI5767/2CB analog section from a clean 5 V LDO (no switching converters on the same rail). Add a 10 µF + 0.1 µF ceramic bypass within 5 mm of each AVDD pin and 1 µF + 0.01 µF at the digital DVDD and driver DRVDD pins. Estimated quiescent current is ~30 mA analog + ~5 mA digital at 40 MSPS, so budget a 0.5 W maximum supply. Include a ferrite bead between analog and digital ground returns on the PCB rather than relying on a single shared ground plane to avoid digital noise coupling into the analog reference.
The encode clock source is critical for jitter-sensitive undersampling applications. Use a 3.3 V CMOS clock generator with jitter below 5 ps rms to avoid degrading SNR. Keep the CLK trace short and 50 ohm-terminated. The analog input should be AC-coupled with a 50 ohm shunt to ground at the AIN pin; for differential inputs add a 1:1 balun upstream. Verify digital-output edge rates and add 22 Ω series damping if the D0-D9 traces exceed 25 mm to a downstream FPGA.
Use a 4-layer PCB with a dedicated analog ground plane and split digital/analog sections under the SOIC-28 footprint. Place a guard ring around the AIN pin connected to AGND to reduce crosstalk. The VREF pin requires a 10 µF + 100 nF bypass with traces under 3 mm to the package; insufficient decoupling on VREF is the most common cause of excess DNL. Avoid running digital output traces directly under the SOIC-28 footprint.
Do not substitute the HI5767/2CB with the HI5767/6CB on a board designed for 40 MSPS without verifying that the downstream FPGA can capture at 60 MSPS and that the clock source has adequate drive strength. For RoHS-critical designs choose the /2CBZ variant for matte-tin finish; older /2CB date codes may use SnPb plating. Because the part is Obsolete, do not design new production boards without second-sourcing to an active ADC family - validated drop-in pin-compatible families include the HI5766KCAZ or TI's ADS901E/1K.
Informations de conformité
Compliance status not explicitly listed in the verified data. The /2CBZ variant typically indicates a lead-free matte-tin finish, but a Certificate of Compliance should be requested from the franchised distributor before PCB assembly for RoHS-critical designs.
