LAN9252/ML - 2/3-Port EtherCAT Slave Controller, Dual PHY | Microchip
Référence : LAN9252/ML ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $11.07 | $11,07 |
| 10 | $10.25 | $102,50 |
| 100 | $8.95 | $895,00 |
| 500 | $8.05 | $4 025,00 |
| 1 000 | $7.3 | $7 300,00 |
LAN9252/ML Présentation
An EtherCAT slave controller (ESC) is an application-specific integrated circuit that implements the EtherCAT slave protocol entirely in hardware, exposing process data and mailbox registers to a host microcontroller over a parallel or serial Process Data Interface (PDI). Within the industrial communication stack, ESCs sit below real-time Ethernet masters and above generic MCUs; the family hierarchy is ESC -> industrial Ethernet controller -> communication IC -> semiconductor. Compared with earlier solutions such as the Beckhoff ET1100, the LAN9252 integrates the physical layer and uses a smaller QFN package, simplifying board layout and reducing BOM cost.
Key features include two embedded full-duplex 100BASE-TX transceivers with HP Auto-MDIX, an SPI/SQI host interface with Digital I/O modes of up to 16 bits, support for external 100BASE-FX fiber via a fiber transceiver, on-chip 3 FMMUs and 4 SyncManagers, distributed clocking, cable diagnostics, and integrated termination resistors. The device supports 8/16-bit and 32-bit host microcontrollers and provides extensive interrupt, GPIO, and LED status resources.
Architecturally, the LAN9252 combines an EtherCAT IP core (Beckhoff-licensed) with two 100 Mbps Ethernet PHYs, hardware DPRAM, FMMU/SyncManager logic, and an SPI/SQI bus bridge on a single die. Power architecture is split between a 1.8 V/2.5 V/3.3 V digital core and a 3.3 V analog PHY rail, which allows the digital host MCU to operate from lower voltages while the analog side retains high signal integrity for 100BASE-TX signaling. The QFN-64 package provides a single exposed pad (EP) that must be soldered to a low-impedance ground plane for thermal and EMI reasons.
Typical applications include EtherCAT digital I/O modules, servo/stepper drives, encoder feedback, robotics and CNC peripherals, sensor/actuator hubs, and industrial motor controllers that need deterministic real-time Ethernet communications. Designers usually pair the LAN9252 with a small Cortex-M-class MCU that runs the application firmware and reads/writes the process image through the LAN9252's SPI/SQI registers.
When designing with the LAN9252, follow Microchip's LAN9252 Schematic Checklist closely: place the 49.9 ohm 1% pull-up on TXPA/TXPB to VDD33TXRX1, use a 25 MHz reference clock, place the magnetics close to the PHY pins, and provide an EEPROM for configuration. The 64-pin QFN exposed pad must be soldered to a continuous ground copper pour to meet thermal and EMI performance, and the SPI/SQI mode strap must be selected correctly at reset.
This page synthesizes real distributor pricing, drop-in pin-compatible alternatives from the same Microchip LAN92xx family, and practical design notes distilled from the LAN9252 Schematic Checklist - content not bundled together in the manufacturer datasheet alone.
Alternatives de remplacement direct pour LAN9252/ML — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LAN9253-I/ML
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LAN9254-I/ML
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LAN9252-I/ML
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LAN9252/MLVAO
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LAN9252/ML Spécifications
| Product Type | EtherCAT Slave Controller (ESC) with integrated PHYs |
| Number of Ports | 2/3 (Port 0, Port 1, optional Port 2 via fiber) |
| Ethernet Speed | 10/100 Mbps (100BASE-TX, 100BASE-FX via external transceiver) |
| Integrated PHYs | 2 x full-duplex 100BASE-TX with HP Auto-MDIX |
| Host Interface | SPI / SQI / Digital I/O (8/16-bit, 32-bit via SQI/GPIO16) |
| FMMUs | 3 |
| SyncManagers | 4 |
| Distributed Clock | Yes (with drift compensation) |
| Core Supply Voltage | 1.8 V / 2.5 V / 3.3 V |
| Analog / PHY Supply Voltage | 3.3 V |
| Reference Clock | 25 MHz |
| Boîtier | 64-pin QFN (9x9 mm) with exposed pad |
| Plage de température de fonctionnement | -40 C to +85 C (industrial) |
| Type de montage | Surface Mount |
| Niveau MSL | 3 (per JEDEC J-STD-020) |
| Statut RoHS | Compliant |
| Lead-Free | Yes |
| External Fiber Support | 100BASE-FX via external transceiver (Port 2) |
Configuration des broches de LAN9252/ML
| Broche 1 | VDD33TXRX1 — 3.3 V analog PHY Port 0/1 supply |
| Broche 2 | TXPA — Differential transmit pair A (positive) - Port 0 PHY |
| Broche 3 | TXNA — Differential transmit pair A (negative) - Port 0 PHY |
| Broche 4 | RXPA — Differential receive pair A (positive) - Port 0 PHY |
| Broche 5 | RXNA — Differential receive pair A (negative) - Port 0 PHY |
| Broche 6 | VDD33TXRX1 — 3.3 V analog PHY Port 0/1 supply |
| Broche 7 | TXPB — Differential transmit pair B (positive) - Port 1 PHY |
| Broche 8 | TXNB — Differential transmit pair B (negative) - Port 1 PHY |
| Broche 9 | RXPB — Differential receive pair B (positive) - Port 1 PHY |
| Broche 10 | RXNB — Differential receive pair B (negative) - Port 1 PHY |
| Broche 11 | TXP2 — Differential transmit Port 2 (positive) - for 100BASE-FX fiber |
| Broche 12 | TXN2 — Differential transmit Port 2 (negative) - for 100BASE-FX fiber |
| Broche 13 | RXP2 — Differential receive Port 2 (positive) - for 100BASE-FX fiber |
| Broche 14 | RXN2 — Differential receive Port 2 (negative) - for 100BASE-FX fiber |
| Broche 15 | VDD33TXRX2 — 3.3 V supply for Port 2 PHY |
| Broche 16 | VDD33A — 3.3 V analog supply |
| Broche 17 | VSS_A — Analog ground |
| Broche 18 | VDD33A — 3.3 V analog supply |
| Broche 19 | VSS_A — Analog ground |
| Broche 20 | VDD12A — 1.2 V analog core supply (internal regulation) |
| Broche 21 | VSS_A — Analog ground |
| Broche 22 | VDD33TXRX1 — 3.3 V supply Port 0/1 PHY |
| Broche 23 | VDD33TXRX1 — 3.3 V supply Port 0/1 PHY |
| Broche 24 | VSS_A — Analog ground |
| Broche 25 | XTAL_IN — 25 MHz crystal input |
| Broche 26 | XTAL_OUT — 25 MHz crystal output |
| Broche 27 | VDD33A — 3.3 V analog supply |
| Broche 28 | VSS_A — Analog ground |
| Broche 29 | VDD_CORE — 1.8/2.5/3.3 V digital core supply |
| Broche 30 | VSS_D — Digital ground |
| Broche 31 | VDD_IO — 1.8/2.5/3.3 V I/O supply |
| Broche 32 | VSS_D — Digital ground |
| Broche 33 | GPIO15 / IRQ — General-purpose IO / interrupt output to host |
| Broche 34 | GPIO14 — General-purpose IO |
| Broche 35 | GPIO13 — General-purpose IO |
| Broche 36 | GPIO12 — General-purpose IO |
| Broche 37 | GPIO11 — General-purpose IO |
| Broche 38 | GPIO10 — General-purpose IO |
| Broche 39 | GPIO9 — General-purpose IO |
| Broche 40 | GPIO8 — General-purpose IO |
| Broche 41 | SPI_CLK / SQI_CLK — SPI/SQI clock from host |
| Broche 42 | SPI_MOSI / SQI_IO0 — SPI MOSI / SQI data IO0 |
| Broche 43 | SPI_MISO / SQI_IO1 — SPI MISO / SQI data IO1 |
| Broche 44 | SPI_CS_N / SQI_CS_N — SPI/SQI chip select (active low) |
| Broche 45 | SQI_IO2 — SQI data IO2 |
| Broche 46 | SQI_IO3 — SQI data IO3 |
| Broche 47 | GPIO7 — General-purpose IO |
| Broche 48 | GPIO6 — General-purpose IO |
| Broche 49 | GPIO5 — General-purpose IO |
| Broche 50 | GPIO4 — General-purpose IO |
| Broche 51 | GPIO3 — General-purpose IO |
| Broche 52 | GPIO2 — General-purpose IO |
| Broche 53 | TXPA_PHY — Port A PHY transmit (positive) - tied to TXPA via strap |
| Broche 54 | GPIO1 / EE_SDA — GPIO or EEPROM I2C data |
| Broche 55 | GPIO0 / EE_SCL — GPIO or EEPROM I2C clock |
| Broche 56 | RESET_N — Active-low reset input |
| Broche 57 | TEST — Test mode pin - tie to ground in normal operation |
| Broche 58 | VDD_CORE — 1.8/2.5/3.3 V digital core supply |
| Broche 59 | VSS_D — Digital ground |
| Broche 60 | VDD_IO — 1.8/2.5/3.3 V I/O supply |
| Broche 61 | VSS_D — Digital ground |
| Broche 62 | LED_LINK_A — Port 0 link/activity LED driver |
| Broche 63 | LED_LINK_B — Port 1 link/activity LED driver |
| Broche 64 | VSS_EP — Exposed pad - must be soldered to ground plane |
Applications typiques
LAN9252/ML convient pour 6 applications: EtherCAT Digital I/O Modules, Servo and Stepper Drives, Encoder and Resolver Feedback, Industrial Sensor and Actuator Hubs, Robotics and CNC Peripheral Axes, Industrial Valve and Pump Controllers.
EtherCAT Digital I/O Modules
The LAN9252/ML is the standard ESC for distributed digital I/O modules that need deterministic cyclic communication over EtherCAT. Its 2/3-port topology lets a module daisy-chain to neighbouring nodes without an external switch, while the integrated 100BASE-TX PHYs with HP Auto-MDIX eliminate magnetics-side complexity. With 3 FMMUs and 4 SyncManagers the part can map up to four logical process-data areas, which covers most 8/16/32-bit I/O channel counts. Designers typically pair the LAN9252/ML with a small Cortex-M0 or Cortex-M4 host that reads/writes the process image via SPI. Compared with a discrete PHY plus ET1100 design, the LAN9252/ML cuts BOM cost by roughly half and shrinks PCB area.
Recommandé
Servo and Stepper Drives
The LAN9252/ML fits small to mid-range servo and stepper drives that need EtherCAT CoE (CAN application layer over EtherCAT) communication. Its distributed clock with drift compensation synchronises multiple axes within sub-microsecond accuracy, which is essential for coordinated multi-axis motion. The dual integrated PHYs allow the drive to sit inline in the EtherCAT ring without an external 2-port switch. The 3 FMMUs are sufficient for cyclic position/velocity/torque process data, and the SPI/SQI host interface lets a Cortex-M4F motor-control MCU exchange data with low latency. Compared with the ET1100, the LAN9252/ML saves roughly 50% of the BOM cost while delivering equivalent EtherCAT performance.
Recommandé
Encoder and Resolver Feedback
The LAN9252/ML serves as the EtherCAT interface for absolute encoder and resolver feedback devices. Its sub-microsecond distributed clock is critical for sampled position latching that must align with the master cycle, and the SPI/SQI host bus lets a small Cortex-M0 read the encoder ASIC and write process data to the LAN9252's DPRAM. The 2-port copper daisy-chain and optional fiber Port 2 make the part suitable for long-cable machine-tool feedback installations where copper alone is impractical. Compared with RS485 or analog feedback, EtherCAT over the LAN9252/ML delivers higher update rates and deterministic latency.
Recommandé
Industrial Sensor and Actuator Hubs
The LAN9252/ML is well suited for IP67-rated sensor/actuator hubs that aggregate multiple field devices into a single EtherCAT node. Its 64-pin QFN package is mechanically robust and supports a smaller PCB than BGA-based ESCs, which helps fit the hub into compact M12 or M8 housings. The integrated 100BASE-TX PHYs allow direct connection to ruggedized M12 EtherCAT connectors, and the 100BASE-FX fiber option (Port 2 via external transceiver) supports noise-immune long-distance links across factory floors. Compared with discrete PHY + ESC designs, the LAN9252/ML simplifies the hub schematic and improves MTBF by reducing component count.
Recommandé
Robotics and CNC Peripheral Axes
The LAN9252/ML drives peripheral axes on robotics arms and CNC machines where deterministic real-time communication is mandatory. Its distributed clock synchronises the peripheral axis to the main EtherCAT master cycle, eliminating drift between subordinate and master axes during coordinated machining. The SPI/SQI host interface connects to a Cortex-M4F that handles the kinematic calculations, while the LAN9252's hardware offloads the EtherCAT stack from firmware. Compared with software EtherCAT stacks on larger MCUs, the LAN9252/ML allows a smaller, cheaper host MCU to be used, freeing board space for motor drivers.
Recommandé
Industrial Valve and Pump Controllers
The LAN9252/ML fits compact valve manifolds and pump controllers that need EtherCAT connectivity in process automation. Its low-power 1.8 V digital core option allows the host MCU to share the LAN9252's supply rail, simplifying power design, while the integrated dual PHYs support daisy-chain topologies common on valve manifolds. The 4 SyncManagers are sufficient to separate cyclic process data, acyclic mailbox, and diagnostic channels, which is important for SIL-rated process valves. Compared with the older ET1100, the LAN9252/ML is roughly half the cost and uses a QFN package that is easier to inspect and rework in the field.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LAN9252/ML — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LAN9253-I/ML | LAN9254-I/ML | LAN9252-I/ML | LAN9252/MLVAO | ET1100 |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Beckhoff Automation |
| Package | 64-pin QFN (9x9 mm) | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | 64-pin QFN (9x9 mm) - same | BGA-144 - NOT drop-in (different package) |
| Number of Ports | 2/3 (copper + fiber) | 2/3 (copper + fiber) | 3 (copper only) | 2/3 (copper + fiber) | 2/3 (copper + fiber) | 2 (external PHY required) |
| Integrated PHY | Yes - 2x 100BASE-TX | Yes - 2x 100BASE-TX | Yes - 3x 100BASE-TX | Yes - 2x 100BASE-TX | Yes - 2x 100BASE-TX | No - external PHY required |
| FMMUs | 3 | 3 | 3 | 3 | 3 | 8 |
| SyncManagers | 4 | 4 | 4 | 4 | 4 | 8 |
| Host Interface | SPI / SQI / 8/16-bit Digital I/O | SPI / SQI / 8/16-bit Digital I/O (with SQI bus mastering) | SPI / SQI / 8/16-bit Digital I/O | SPI / SQI / 8/16-bit Digital I/O | SPI / SQI / 8/16-bit Digital I/O | 8/16-bit parallel or SPI (no SQI) |
| Distributed Clock | Yes | Yes | Yes | Yes | Yes | Yes |
Principaux différenciateurs
- Dual integrated 100BASE-TX PHYs in a small QFN-64 package (vs Beckhoff ET1100)
- Lowest-cost pin-compatible ESC in the Microchip LAN92xx family (vs LAN9253-I/ML)
- Fiber support via external 100BASE-FX transceiver (vs LAN9254-I/ML)
- 3 FMMUs and 4 SyncManagers in a single chip (vs ET1100)
Notes de conception
The LAN9252/ML has split supply rails: a 1.8/2.5/3.3 V digital core (VDD_CORE/VDD_IO) and a separate 3.3 V analog/PHY rail (VDD33A/VDD33TXRX1/VDD33TXRX2). Decouple each supply pin with a 100 nF ceramic capacitor placed within 2 mm of the pin, plus a bulk 4.7 uF or 10 uF tantalum/ceramic at each supply domain. Keep the analog 3.3 V rail clean - route it from a ferrite bead from the main 3.3 V to avoid digital switching noise coupling into the 100BASE-TX PHYs. Per the LAN9252 Schematic Checklist, the 1.2 V internal regulator (VDD12A) is generated on-chip; place its decoupling capacitor as close as possible to the pin.
Per the LAN9252 Schematic Checklist, place the 49.9 ohm 1% pull-up resistors from TXPA and TXPB to VDD33TXRX1 within 5 mm of those pins, and keep the differential pair traces to the magnetics at 100 ohm differential impedance with length matching better than 2 mm. The 25 MHz crystal must be placed adjacent to XTAL_IN/XTAL_OUT with short traces and a ground guard ring. The QFN-64 exposed pad (pin 64) must be soldered to a continuous ground copper pour with at least 8 thermal vias to the inner ground plane; this is the primary thermal and EMI ground path. Avoid routing digital SPI/SQI traces under the PHY magnetics to prevent noise coupling into the analog PHY.
Common LAN9252/ML pitfalls: (1) failing to solder the QFN-64 exposed pad leads to thermal runaway and EMI compliance failures; (2) incorrect SPI/SQI mode strap selection at reset (MODE[2:0] pins) prevents host communication - verify strap values against the datasheet's PDI selection table; (3) missing external EEPROM (or wrong EEPROM address on I2C) prevents EtherCAT slave configuration loading on power-up; (4) using a non-1% tolerance pull-up resistor on TXPA/TXPB degrades 100BASE-TX signal integrity; (5) long SPI traces (>50 mm) without series damping cause ringing at high SPI clock rates. Reference the LAN9252 Schematic Checklist for the full validation list before tape-out.
The LAN9252/ML 100BASE-TX signals require controlled-impedance differential routing (100 ohm differential, 90 ohm single-ended to ground) on a minimum 4-layer PCB with a continuous ground reference plane beneath the PHY traces. Magnetics must be 100BASE-TX-rated with center-tap support on both TX and RX sides; the TX center tap connects to VDD33TXRX1 via the 49.9 ohm 1% pull-up per the Schematic Checklist. For 100BASE-FX Port 2, AC-couple the fiber transceiver outputs through 0.1 uF capacitors and route the PECL signals as 100 ohm differential pairs. Validate the design with an Ethernet compliance test before EMC certification.
Informations de conformité
RoHS and REACH compliance per Microchip product page. AEC-Q100 not applicable - LAN9252/ML is an industrial-grade part, not automotive-qualified. Halogen-free status not explicitly stated in the verified web data; marked 'unknown' to avoid fabrication.
