LTC2170IUKG-12 - 12-Bit 25Msps Quad ADC | Analog Devices
Référence : LTC2170IUKG-12 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $28.95 | $2 895,00 |
| 500 | $24.2 | $12 100,00 |
| 1 000 | $21.4 | $21 400,00 |
LTC2170IUKG-12 Présentation
What is a quad ADC? A quad ADC is an integrated circuit that contains four matched ADC cores and a shared reference, clock, and digital interface. By integrating four converters into one package, the quad ADC removes channel-to-channel timing skew and simplifies PCB routing for multi-channel data acquisition systems. A pipelined ADC converts an analog input by passing the sampled voltage through a cascade of low-resolution stages, producing a high throughput at moderate resolution. Quad ADCs sit inside the hierarchy of data-converter ICs -> ADC -> high-speed ADC -> pipelined ADC -> simultaneous-sampling ADC -> semiconductor.
Key features of the LTC2170-12 include 71 dB SNR and 90 dB spurious-free dynamic range (SFDR), 0.15 ps RMS aperture jitter for accurate undersampling of IF signals, and an 800 MHz full-power input bandwidth. The serial LVDS digital interface supports both 1-lane (one bit per channel per cycle) and 2-lane (two bits per channel per cycle) modes, minimizing the number of board traces between the ADC and the FPGA/ASIC. A serial SPI port configures output mode, input range, and channel shutdown. Selectable input ranges of 1 Vp-p to 2 Vp-p enable direct connection to most IF and baseband drivers without external attenuators.
Typical applications include multi-channel communications receivers, phased-array antenna digitizers, medical imaging front ends, and industrial ultrasound beamformers. The wide input bandwidth and low jitter also make the part well suited to undersampling of intermediate-frequency signals in software-defined radio (SDR) platforms.
When designing with this part, follow the recommended layout in the manufacturer datasheet: keep analog input traces length-matched and surrounded by a continuous ground plane, place the 1.8 V supply decoupling within 5 mm of the ADJ pin, and route the LVDS pairs as 100 ohm differential lines to the FPGA. The exposed pad (EP) on the bottom of the QFN must be soldered to a ground pad for thermal and electrical performance.
Alternatives de remplacement direct pour LTC2170IUKG-12 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LTC2170IUKG-12 (même facteur de forme et même empreinte) — différant par Package, Resolution, Input Type, Supply Voltage, Architecture.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LTC2170CUKG-12
✅ Remplacement direct✓ En stock
$20.65 / unité
Voir la fiche technique →LTC2171IUKG-12
✅ Remplacement direct✓ En stock
$23.3 / unité
Voir la fiche technique →LTC2172IUKG-12
✅ Remplacement direct✓ En stock
$33.1 / unité
Voir la fiche technique →LTC2170IUKG-14
✅ Remplacement direct✓ En stock
$45.83 / unité
Voir la fiche technique →LTC2171CUKG-12
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$24 / unité
Voir la fiche technique →LTC2170IUKG-12 Valeurs maximales et caractéristiques électriques
| Résolution | 12 bits |
| Number of Channels | 4 |
| Sampling Rate (per channel) | 25 Msps |
| Architecture | Pipelined, simultaneous sampling |
| SNR | 71 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.15 ps RMS |
| Full-Power Input Bandwidth | 800 MHz |
| INL (typical) | 0.3 LSB |
| DNL (typical) | 0.1 LSB |
| Transition Noise | 0.3 LSB RMS |
| Input Range (selectable) | 1 Vp-p to 2 Vp-p |
| Digital Output | Serial LVDS, 1-lane or 2-lane |
| Configuration Interface | Serial SPI |
| Tension d'alimentation | 1.8 V single supply |
| Total Power (25 Msps) | 160 mW |
| Per-Channel Power | 40 mW |
| Plage de température de fonctionnement | -40C to +85C (I grade) |
| Boîtier | 52-pin QFN-EP (7 mm x 8 mm) |
| Type de montage | Surface Mount |
| Pin-Compatible Family Members | LTC2172-12 (65 Msps), LTC2171-12 (40 Msps), LTC2170-12 (25 Msps), LTC2170-14 (14-bit) |
| Statut RoHS | Compliant |
Guide de configuration des broches du LTC2170IUKG-12 52-pin qfn-ep (7 mm x 8 mm)
Configuration des broches du LTC2170IUKG-12 (boîtier 52-pin qfn-ep (7 mm x 8 mm)). Ce composant analogique comporte des broches d'entrée, de sortie et d'alimentation. Consultez la fiche technique du fabricant pour les configurations des broches d'annulation d'offset, de compensation et d'activation. Idéal pour le conditionnement de signaux et les circuits amplificateurs.
Aucune donnée de brochage détaillée disponible pour LTC2170IUKG-12.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
LTC2170IUKG-12 convient pour 6 applications: Multi-Channel Communications Receiver, Phased-Array Antenna Digitizer, Industrial Ultrasound Beamformer, Software-Defined Radio (SDR) Front End, Test and Measurement Instrumentation, Data Acquisition Card for Industrial Automation.
Multi-Channel Communications Receiver
The LTC2170IUKG-12 is designed for multi-channel communications receivers where four matched ADCs digitize I/Q baseband or IF signals in parallel. Its 800 MHz full-power bandwidth and 0.15 ps RMS aperture jitter allow accurate undersampling of IF frequencies above the 25 Msps Nyquist rate, while 71 dB SNR and 90 dB SFDR preserve modulation fidelity for QAM and OFDM signals. Per-channel power is only 40 mW from a single 1.8 V supply, which is critical for dense multi-antenna receiver cards. The serial LVDS interface minimizes board traces, simplifying layout on crowded receiver boards. Pairs naturally with an Analog Devices ADF4350 or ADF4106 PLL synthesizer for the local oscillator.
Recommandé
Phased-Array Antenna Digitizer
Phased-array antennas require simultaneous sampling of multiple antenna elements with precise channel-to-channel phase alignment. The LTC2170IUKG-12's matched four-channel architecture and shared clock tree eliminate the timing skew that discrete ADCs would introduce, while its 12-bit resolution and 71 dB SNR provide sufficient dynamic range for digital beamforming. The 25 Msps rate supports narrowband radar and 5G FR1 beamforming up to about 12 MHz of baseband bandwidth per channel. The 52-pin QFN-EP package's small 7x8 mm footprint lets designers place the ADC close to the antenna feed, reducing trace length and improving noise performance.
Recommandé
Industrial Ultrasound Beamformer
Ultrasound beamforming systems digitize 32 to 256 transducer channels and combine them with precise time delays to form an image. The LTC2170IUKG-12's 4-channel simultaneous sampling with sub-picosecond aperture jitter preserves the relative phase information required for accurate beamforming. Its 71 dB SNR is adequate for mid-range diagnostic ultrasound, while 40 mW per channel helps meet the thermal budget of a dense multi-channel PCB. The serial LVDS interface lets the system designer route the digitized RF back to a central FPGA with far fewer board traces than parallel CMOS ADCs, simplifying layout in cramped probe heads.
Recommandé
Software-Defined Radio (SDR) Front End
Software-defined radio platforms digitize as much of the signal chain as possible to push demodulation into software. The LTC2170IUKG-12's 800 MHz full-power input bandwidth and 0.15 ps RMS aperture jitter enable direct undersampling of intermediate-frequency signals in the 50 MHz to 200 MHz range without a separate downconversion stage. Its 12-bit resolution and 90 dB SFDR preserve the wide dynamic range required for dense urban RF environments. The four-channel input supports diversity receivers or multi-band capture, and the 25 Msps rate keeps the data rate manageable for downstream FPGA or DSP processing.
Recommandé
Test and Measurement Instrumentation
Bench-top oscilloscopes, spectrum analyzers, and digitizers require multi-channel acquisition with calibrated phase relationships and low noise. The LTC2170IUKG-12's 71 dB SNR, 90 dB SFDR, and matched four-channel architecture deliver the AC performance needed for production-line ATE and laboratory instruments. Its SPI-programmable input range (1 Vp-p to 2 Vp-p) and shutdown modes simplify integration into modular instruments where channel count and input scaling vary by configuration. The 1.8 V single-supply operation keeps the analog front-end power budget predictable across the 25 Msps to 65 Msps pin-compatible family.
Recommandé
Data Acquisition Card for Industrial Automation
Multi-channel data acquisition cards in industrial automation must sample several analog signals with precise timing and feed the digitized data to an FPGA or processor. The LTC2170IUKG-12's four simultaneous-sampling 25 Msps channels provide 100 Msps aggregate throughput in a single 52-pin QFN-EP package, eliminating the need for four discrete ADCs. Its 0.3 LSB transition noise and no-missing-codes performance over temperature make it reliable for process-control loops that operate across -40C to +85C industrial environments. The serial LVDS interface is highly resistant to common-mode noise in electrically noisy factory floors.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LTC2170IUKG-12 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LTC2170CUKG-12 | LTC2171IUKG-12 | LTC2172IUKG-12 | LTC2170IUKG-14 | LTC2171CUKG-12 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 52-pin QFN-EP (7x8 mm) | 52-pin QFN-EP (7x8 mm) - same | 52-pin QFN-EP (7x8 mm) - same | 52-pin QFN-EP (7x8 mm) - same | 52-pin QFN-EP (7x8 mm) - same | 52-pin QFN-EP (7x8 mm) - same |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits | 12 bits |
| Sampling Rate (per channel) | 25 Msps | 25 Msps | 40 Msps | 65 Msps | 25 Msps | 40 Msps |
| Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| SNR | 71 dB | 71 dB | 70.5 dB | 70 dB | 73.5 dB | 70.5 dB |
| SFDR | 90 dB | 90 dB | 88 dB | 85 dB | 88 dB | 88 dB |
| Total Power at Rated Speed | 160 mW | 160 mW | 198 mW | 306 mW | 160 mW | 198 mW |
| Operating Temperature Range | -40C to +85C (I grade) | 0C to +70C (C grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | -40C to +85C (I grade) | 0C to +70C (C grade) |
Principaux différenciateurs
- Lowest power in the LTC2172/LTC2171/LTC2170 family (vs LTC2171IUKG-12 and LTC2172IUKG-12)
- Industrial temperature grade for harsh environments (vs LTC2170CUKG-12)
- Simultaneous sampling across all four channels (vs Discrete multi-ADC designs (e.g. four individual 12-bit ADCs))
Notes de conception
Route the four analog inputs as length-matched 50-ohm single-ended traces (or 100-ohm differential pairs if driving differentially) directly to the ADC pins. Keep input traces short and surround them with a continuous ground plane on the top layer. According to the manufacturer datasheet, the analog input traces must be kept away from the LVDS output traces and the SPI configuration lines to avoid digital-to-analog coupling. The exposed pad (EP) of the 52-pin QFN must be soldered to a ground pad with at least 8 thermal vias for thermal and electrical performance.
Place a 1 uF X7R ceramic decoupling capacitor within 5 mm of the ADJ (1.8 V analog supply) pin and a 0.1 uF X7R capacitor within 2 mm. Add a 10 uF bulk capacitor on the same rail. Use a ferrite bead to isolate the analog 1.8 V supply from any digital 1.8 V supply that feeds the FPGA or ASIC. The clock and LVDS outputs draw switching current, so a separate filtered AVCC rail reduces jitter. The total power at 25 Msps is 160 mW (40 mW per channel), so a small LDO is sufficient and a switching regulator upstream is acceptable if its switching noise is below the ADC's PSRR.
Treat the LVDS output pairs as 100-ohm differential controlled-impedance lines. Route each LVDS pair with constant spacing and length-matching within 5 ps to avoid inter-symbol skew at the FPGA receiver. Place the LVDS series termination resistors (typically 100 ohms across the pair) at the FPGA end, not at the ADC end. Keep the SPI configuration lines short and away from the LVDS pairs. According to the manufacturer datasheet, the clock input is a differential pair and should be routed as such to preserve the 0.15 ps RMS aperture jitter specification.
The 800 MHz full-power input bandwidth means the ADC will alias any high-frequency noise on the analog inputs into the baseband. Estimated: with -40 dBm of noise on the analog input above 100 MHz, the aliased in-band SNR degradation is approximately 1.5 dB. Place an antialiasing filter (typically a 3rd-order L-C or active filter) on each channel before the ADC input. The filter cutoff should be set above the highest input frequency of interest (typically 0.4 x Fs for Nyquist sampling, or higher for undersampling).
Common pitfalls include: (1) forgetting to solder the exposed pad (EP) of the QFN - this degrades thermal performance and ground return; (2) driving the analog input with a single-ended signal when the input is configured for differential - this halves the input range and degrades SFDR; (3) not programming the input range through SPI - register jumps from 1 Vp-p to 2 Vp-p must be set explicitly; (4) leaving the SPI port floating at power-up - the ADC defaults to a specific configuration, but floating SDI can cause bit errors; (5) using a 12-bit ADC where 14-bit is needed - the LTC2170IUKG-14 is a drop-in upgrade on the same PCB.
Informations de conformité
RoHS and lead-free confirmed by Analog Devices product page. Not AEC-Q100 qualified; for automotive, consider higher-grade parts. Halogen-free status not stated in available data - flagged as unknown.
