LTC2273IUJ - 16-Bit 80Msps Serial JESD204 ADC | Analog Devices
Référence : LTC2273IUJ ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $42.5 | $42,50 |
| 10 | $38.25 | $382,50 |
| 100 | $34.1 | $3 410,00 |
| 500 | $30.85 | $15 425,00 |
| 1 000 | $27.4 | $27 400,00 |
LTC2273IUJ Présentation
An ADC (Analog-to-Digital Converter) is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes. High-speed pipelined ADCs like the LTC2273 sit between the analog front end (sensor, amplifier, filter) and the digital signal processor or FPGA, with sample rates from tens of megasamples per second to gigasamples per second. They are members of the data converter IC family within the broader signal chain hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The 16-bit resolution provides 65536 discrete codes, enabling wide dynamic range capture.
Key features include 80Msps sampling rate (65Msps for the pin-compatible LTC2272), 700 MHz input bandwidth for undersampling of IF signals, programmable input range via the PGA front end, JESD204 serial output for board-area reduction, and 40-lead QFN package. The PGA optimizes the input range for maximum SNR across diverse signal amplitudes. Operating from a 3.3V supply, the part dissipates approximately 1.4W during full-speed conversion and supports an industrial -40C to +85C temperature range.
The pipelined architecture uses multi-stage switched-capacitor gain stages with digital error correction, achieving 77 dBFS SNR and 90 dBc SFDR at 30 MHz input. The JESD204 serial interface transmits data over 1 to 2 lanes at up to 3.2 Gbps per lane, providing deterministic latency and eliminating wide parallel data buses between the ADC and the FPGA/ASIC. The 700 MHz input bandwidth supports undersampling of IF frequencies, simplifying receiver architectures by eliminating a downconversion stage.
Typical applications include cellular base-station receivers (LTE, WCDMA, GSM), software-defined radio (SDR), digital oscilloscopes, radar and lidar systems, medical imaging, and cable modems. The combination of high input bandwidth, JESD204 output, and 16-bit resolution is well suited to multi-carrier, multi-standard communications infrastructure where dynamic range and channel density matter.
When designing with this part, provide a low-jitter clock source (<200 fs RMS) to preserve SNR at high input frequencies. Decouple AVDD and DVDD supplies separately with 10uF and 0.1uF ceramic capacitors placed within 5 mm of the supply pins. Route the JESD204 serial lanes as 100 ohm differential pairs, length-matched to within 5 mils, and keep them isolated from noisy digital returns.
This page synthesizes the manufacturer datasheet, real distributor pricing, JESD204 pin-compatible alternatives from the LTC226x family, and practical PCB-layout notes not found on the manufacturer's product page, giving an engineer one consolidated reference for design-in.
Alternatives de remplacement direct pour LTC2273IUJ — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LTC2273IUJ (même facteur de forme et même empreinte) — différant par Package, Resolution, Output Interface, Number of Channels, RoHS Status.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LTC2272IUJ
✅ Remplacement direct✓ En stock
$22.1 / unité
Voir la fiche technique →LTC2267IUJ-14
✅ Remplacement direct✓ En stock
$31.2 / unité
Voir la fiche technique →LTC2266CUJ-12
✅ Remplacement direct✓ En stock
$11.5 / unité
Voir la fiche technique →LTC2263IUJ-14
✅ Remplacement direct✓ En stock
$18.25 / unité
Voir la fiche technique →LTC2260IUJ-12
✅ Remplacement direct✓ En stock
$11.75 / unité
Voir la fiche technique →LTC2273IUJ Valeurs maximales et caractéristiques électriques
| Manufacturer | Analog Devices (formerly Linear Technology) |
| Part Number | LTC2273IUJ |
| Description | 16-Bit, 80Msps/65Msps Serial Output ADC with JESD204 interface |
| Résolution | 16 bits |
| Sample Rate (LTC2273) | 80 Msps |
| Sample Rate (LTC2272) | 65 Msps |
| Input Bandwidth | 700 MHz |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Output Interface | JESD204 (JEDEC serial interface for data converters) |
| Tension d'alimentation | 3.3 V |
| Boîtier | 40-pin QFN (6x6 mm) with exposed pad |
| Type de montage | Surface Mount |
| Température de fonctionnement | -40C to +85C (Industrial grade, 'I' suffix) |
| Power Dissipation | ~1.4 W at 80 Msps (typical) |
| Input Range | Programmable via PGA front end |
| Statut RoHS | Compliant (PBF suffix denotes lead-free) |
Configuration des broches de LTC2273IUJ
| Broche 1 | GND — Ground |
| Broche 2 | AIN+ — Differential analog input positive |
| Broche 3 | AIN- — Differential analog input negative |
| Broche 4 | GND — Ground |
| Broche 5 | VCM — Common-mode voltage output |
| Broche 6 | REFT — Top reference decoupling |
| Broche 7 | REFB — Bottom reference decoupling |
| Broche 8 | GND — Ground |
| Broche 9 | AVDD — Analog 3.3V supply |
| Broche 10 | GND — Ground |
| Broche 11 | ENC+ — Encode (clock) input positive |
| Broche 12 | ENC- — Encode (clock) input negative |
| Broche 13 | GND — Ground |
| Broche 14 | CS — Chip select (SPI configuration) |
| Broche 15 | SCK — Serial configuration clock (SPI) |
| Broche 16 | SDI — Serial configuration data input (SPI) |
| Broche 17 | SDO — Serial configuration data output (SPI) |
| Broche 18 | GND — Ground |
| Broche 19 | OVDD — Output driver supply |
| Broche 20 | GND — Ground |
| Broche 21 | JESD204_OUT+ — JESD204 serial data output positive (lane 0) |
| Broche 22 | JESD204_OUT- — JESD204 serial data output negative (lane 0) |
| Broche 23 | GND — Ground |
| Broche 24 | NC — Not connected (per datasheet) |
| Broche 25 | GND — Ground |
| Broche 26 | MODE — Mode selection pin |
| Broche 27 | GND — Ground |
| Broche 28 | AVDD — Analog 3.3V supply |
| Broche 29 | GND — Ground |
| Broche 30 | REFT — Top reference decoupling |
| Broche 31 | REFB — Bottom reference decoupling |
| Broche 32 | GND — Ground |
| Broche 33 | VCM — Common-mode voltage output |
| Broche 34 | GND — Ground |
| Broche 35 | AIN+ — Differential analog input positive |
| Broche 36 | AIN- — Differential analog input negative |
| Broche 37 | GND — Ground |
| Broche 38 | AVDD — Analog 3.3V supply |
| Broche 39 | GND — Ground |
| Broche 40 | GND — Ground (exposed pad) |
Applications typiques
LTC2273IUJ convient pour 6 applications: Cellular Base Station Receiver, Software Defined Radio (SDR), Digital Oscilloscope and Test Equipment, Radar and Lidar Signal Processing, Medical Imaging Systems, Cable Modem and Broadband Receiver.
Cellular Base Station Receiver
The LTC2273IUJ fits cellular base-station receivers (LTE, WCDMA, GSM, 5G NR sub-6 GHz) because its 700 MHz analog input bandwidth enables direct IF sampling of multi-carrier signals at carrier frequencies of 70-350 MHz without an analog downconversion stage. The 16-bit resolution captures the wide dynamic range required for simultaneous multi-carrier power amplifier linearization and crest-factor handling. The JESD204 serial interface streams 16-bit samples over one or two lanes at up to 3.2 Gbps per lane into FPGAs such as Xilinx Kintex-7 or Altera/Intel Cyclone V, reducing board complexity versus wide parallel data buses. At 80 Msps the part supports LTE 20 MHz channels and several WCDMA carriers simultaneously, with 77 dBFS SNR delivering the dynamic range needed for receiver sensitivity specifications.
Recommandé
Software Defined Radio (SDR)
For software-defined radio platforms the LTC2273IUJ offers 80 Msps and 700 MHz input bandwidth, allowing direct digitization of IF signals from RF tuners across HF, VHF, and UHF bands. The wide bandwidth supports undersampling architectures that place the ADC clock lower than the input signal frequency, simplifying the analog front end while preserving signal integrity. The JESD204 interface ensures deterministic latency, which is essential for phase-coherent multi-channel SDR and direction-finding applications. The 40-pin QFN package fits compact SDR enclosures used in manpack and vehicular radio systems. Designers can pair the part with an FPGA running DSP algorithms such as channelization, demodulation, and encryption, with the high dynamic range enabling simultaneous strong-signal and weak-signal reception.
Recommandé
Digital Oscilloscope and Test Equipment
The LTC2273IUJ is well suited to mid-range digital oscilloscopes and bench-top test instrumentation that require 16-bit vertical resolution. The 700 MHz input bandwidth supports signal capture on repetitive and single-shot waveforms in the 100 MHz+ range, with the 80 Msps sample rate sufficient for equivalent-time sampling oscilloscopes. The JESD204 interface streams samples into an FPGA for triggering, decimation, and display processing, and the pipelined architecture delivers low aperture jitter for accurate timing measurements. Industrial and scientific test instruments benefit from the part's wide temperature range and lead-free RoHS compliance, which simplify certification of finished equipment for laboratory and field use.
Recommandé
Radar and Lidar Signal Processing
In radar and lidar receivers the LTC2273IUJ's 700 MHz input bandwidth allows direct digitization of IF outputs from RF mixers in pulsed-Doppler, FMCW, and frequency-modulated continuous-wave radar systems. The 80 Msps sample rate captures Doppler spreads up to 40 MHz while the 16-bit resolution handles the dynamic range between large clutter returns and small moving targets. The JESD204 interface supports multi-channel synchronization across phased-array antennas, where deterministic latency from multiple LTC2273IUJ devices enables coherent beamforming. The exposed-pad QFN package provides the thermal headroom needed for continuous-duty radar operation, and the part's industrial temperature range suits outdoor field-deployed systems.
Recommandé
Medical Imaging Systems
The LTC2273IUJ fits medical imaging front ends such as ultrasound and PET detector electronics where 16-bit resolution and a wide dynamic range are essential. In ultrasound receivers, the 700 MHz input bandwidth captures the wideband echo signals returning from deep tissue, while 80 Msps sample rate supports modern multi-channel beamforming systems. The JESD204 serial interface consolidates data from multiple transducers into a single FPGA for image reconstruction, reducing board space inside portable cart-based ultrasound units. The 40-pin QFN exposed-pad package provides reliable thermal performance in continuously running clinical equipment, and the wide operating temperature range simplifies equipment certification for hospital environments.
Recommandé
Cable Modem and Broadband Receiver
The LTC2273IUJ supports cable modem head-end receivers and broadband infrastructure, where the 700 MHz input bandwidth covers downstream DOCSIS channels from 54 MHz to 1 GHz. Direct digitization of multiple QAM channels is feasible at 80 Msps, with the 16-bit resolution handling the high peak-to-average ratio of orthogonal frequency-division-multiplexed signals. The JESD204 interface streams samples into a downstream modem SoC or FPGA, and the industrial temperature range suits outdoor head-end equipment in central office environments. The lead-free QFN package aids compliance with consumer-broadband equipment directives on hazardous substances.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LTC2273IUJ — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LTC2272IUJ | LTC2267IUJ-14 | LTC2266CUJ-12 | LTC2263IUJ-14 |
|---|---|---|---|---|---|
| Package | 40-pin QFN (6x6 mm) | 40-pin QFN (6x6 mm) - same | 40-pin QFN (6x6 mm) - same | 40-pin QFN (6x6 mm) - same | 40-pin QFN (6x6 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 16 bit | 16 bit | 14 bit | 12 bit | 14 bit |
| Sample Rate | 80 Msps | 65 Msps | 105 Msps | 105 Msps | 125 Msps |
| Input Bandwidth | 700 MHz | 700 MHz | 700 MHz | 700 MHz | 700 MHz |
| Output Interface | JESD204 | JESD204 | JESD204 | JESD204 | JESD204 |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) |
Principaux différenciateurs
- JESD204 serial output in a compact 40-pin QFN (vs Parallel-output ADCs such as ADS58C28IRGC25)
- Highest available resolution within the LTC226x / LTC227x 40-pin QFN family at 80 Msps (vs LTC2267IUJ-14 (14-bit at 105 Msps))
- 700 MHz input bandwidth for direct IF sampling (vs LTC2221CUP (lower-bandwidth 12-bit ADC))
Notes de conception
Route the JESD204 differential output lanes (JESD204_OUT+, JESD204_OUT-) as 100 ohm differential microstrip or stripline, length-matched to within 5 mils across the entire pair. Place the LTC2273IUJ close to the receiving FPGA to minimize lane length, and avoid routing the lanes parallel to noisy digital traces or switching power supply lines; keep at least 3W spacing from other signals to limit crosstalk.
Decouple AVDD and OVDD with 10uF X7R ceramic capacitors in parallel with 0.1uF X7R capacitors placed within 5 mm of each supply pin. Use a ferrite bead between the analog and digital 3.3V rails to isolate ADC switching noise from the analog front end. Avoid sharing supply-trace inductance between AVDD pins; each pin should have its own low-impedance path to the bulk capacitor.
Clock jitter above 200 fs RMS directly degrades SNR at high analog input frequencies; use a low-jitter clock driver such as the LTC6953 or a clean crystal-based oscillator, and place the clock trace away from the analog input traces. Do not exceed the maximum encode rate (80 Msps for LTC2273, 65 Msps for LTC2272). The exposed thermal pad must be soldered to a continuous ground plane for rated thermal performance.
Drive the analog input (AIN+, AIN-) differentially with an amplifier such as the LTC6409 or a transformer-coupled balun; single-ended drive reduces SNR by approximately 3 dB and degrades SFDR. The 700 MHz input bandwidth supports under-sampling of IF signals, but the input network must present 100 ohm differential impedance across the target IF band to limit reflections.
Informations de conformité
PBF suffix indicates lead-free / RoHS-compliant finish. JEDEC JESD204 interface per JESD204 spec referenced in datasheet 22732fa. AEC-Q100 not applicable (industrial-grade, not automotive-qualified). Halogen-free status not explicitly stated in verified data.
