M88RT61632 - 16-lane PCIe 6.x/CXL 3.x Retimer, 64 GT/s PAM4 | Montage Technology
Référence : M88RT61632 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $168 | $1 680,00 |
| 100 | $152.5 | $15 250,00 |
| 500 | $138 | $69 000,00 |
| 1 000 | $124.75 | $124 750,00 |
M88RT61632 Présentation
A retimer is a signal-conditioning device placed in the middle of a high-speed serial link to re-clock and equalize degraded signals, restoring signal integrity across long PCB traces, cables, or connector paths. The M88RT61632 sits in the PCI Express / Compute Express Link physical layer stack — PCIe 6.x uses PAM4 modulation at 64 GT/s, doubling the bandwidth of PCIe 5.0 NRZ 32 GT/s. Retimers are increasingly required in AI server fabrics where GPU-to-GPU and GPU-to-CXL-memory links traverse long channels inside the chassis.
Key features include 16 lanes of PCIe 6.x/CXL 3.x with per-lane PAM4 64 GT/s operation, link budget above 40 dB, low-latency retransmission, and compatibility with mainstream industry packaging. Montage's proprietary SerDes IP supports the FLIT-mode framing and FEC structures defined in the PCIe 6.x specification, ensuring full compliance with the PCI-SIG and CXL-3.x standards.
Architecturally, the chip integrates analog front-ends with CTLE, DFE, and adaptation engines, plus protocol-aware PCS layers for PCIe and CXL. The 40+ dB link budget enables signal recovery across long channels, connectors, and backplane routes typically encountered in AI accelerator trays, GPU risers, and CXL memory expansion boards.
Typical applications include AI training and inference servers, CXL memory pooling and expansion, GPU-to-GPU and GPU-to-NVMe interconnects, PCIe switch fabrics, and cloud-computing accelerator sleds. It pairs naturally with leading-edge host processors and switching SoCs that expose PCIe 6.x or CXL 3.x ports.
When designing with the M88RT61632, follow Montage's reference layout guidelines for the SerDes ball map and power-rail decoupling. Provide low-impedance supply rails and isolated analog/digital grounds to maintain the 64 GT/s link budget. Confirm firmware is loaded via the host BMC or system management interface during bring-up.
This page synthesizes manufacturer specifications, distributor availability, and PCB design considerations for engineers evaluating the M88RT61632 in next-generation AI server and CXL memory platforms — information not consolidated in the manufacturer brief alone.
Alternatives de remplacement direct pour M88RT61632 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
M88RT51632
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
M88RT61632 Spécifications
| Product Type | PCIe 6.x / CXL 3.x Retimer |
| Number of Lanes | 16 |
| Data Rate per Lane | Up to 64 GT/s (PAM4) |
| PCIe Specification Compliance | PCIe 6.x |
| CXL Specification Compliance | CXL 3.x |
| Modulation | PAM4 (PCIe 6.x FLIT mode) |
| Link Budget | Above 40 dB |
| SerDes IP | Montage proprietary PAM4 SerDes |
| Generation | 3rd generation retimer |
| Package Type | BGA (mainstream industry package) |
| Type de montage | Surface Mount |
| Target Application | AI servers, cloud computing, CXL memory |
| Status | Sampling |
| Sampling Announced | January 2025 |
Guide de configuration des broches du M88RT61632 bga (mainstream industry package)
Configuration des broches du M88RT61632 (boîtier bga (mainstream industry package)). La numérotation des broches, les fonctions et les schémas de connexion sont définis dans la fiche technique du fabricant. Consultez-la pour l'empreinte exacte et les directives de soudage.
Aucune donnée de brochage détaillée disponible pour M88RT61632.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
M88RT61632 convient pour 6 applications: AI Training Server GPU Interconnect, CXL 3.x Memory Pooling and Expansion, PCIe 6.x Switch Fabric Backplane, NVMe Storage Array PCIe 6.x Attach, AI Accelerator Sled to Host Fabric, Cloud Server PCIe 6.x Riser Card.
AI Training Server GPU Interconnect
The M88RT61632 retimer conditions PCIe 6.x / CXL 3.x signals between GPUs in AI training racks where trace lengths exceed standard motherboard routing budgets. With 16 lanes at 64 GT/s PAM4 and >40 dB link budget, the chip reliably recovers signals across long riser cards and high-density accelerator backplanes common in NVIDIA, AMD, and custom ASIC GPU fabrics. The low-latency retransmission preserves GPU-to-GPU synchronization critical for distributed training jobs. System architects place one retimer per x16 riser slot to extend reach beyond the natural PCIe 6.x FR4 channel limit while maintaining FLIT-mode framing and FEC compliance per the PCI-SIG 6.x specification.
Recommandé
CXL 3.x Memory Pooling and Expansion
The M88RT61632 enables CXL 3.x memory expansion across pooled DDR5 modules attached via long channels inside a rack. CXL 3.x rides on PCIe 6.x physical layer with 64 GT/s PAM4, and the M88RT61632's >40 dB link budget preserves signal integrity across pooled-memory backplanes. Memory pooling at rack scale requires consistent latency across many endpoints; the chip's low-latency retransmission maintains deterministic CXL.mem and CXL.cache coherence. Memory architects deploy one retimer per CXL Type-3 device slot to enable terabyte-scale pooled memory for AI inference and in-memory database workloads.
Recommandé
PCIe 6.x Switch Fabric Backplane
The M88RT61632 acts as a signal-conditioning bridge inside PCIe 6.x switch fabrics and backplanes used in hyperscale cloud servers. With 16 lanes at 64 GT/s PAM4, a single retimer compensates for signal loss across multi-meter backplane traces and multiple high-density connectors. The proprietary PAM4 SerDes adapts continuously via CTLE and DFE equalization, maintaining link-margin headroom under temperature variation. Cloud architects use one retimer per switch-card interface to extend PCIe 6.x reach from host CPU to edge accelerators without compromising the 64 GT/s data rate.
Recommandé
NVMe Storage Array PCIe 6.x Attach
The M88RT61632 conditions PCIe 6.x signals between an NVMe storage controller and high-density EDSFF E1.S / E3.S drives across long backplane traces. NVMe-oF storage tiers increasingly require 64 GT/s PAM4 throughput, and the chip's link budget above 40 dB ensures error-free operation across dense drive bays with multiple mid-plane connectors. The retimer's low-latency design preserves the deterministic IOPS characteristics required for tier-0 storage workloads in AI data lakes. Storage architects integrate one retimer per backplane segment to deliver full PCIe 6.x bandwidth to every EDSFF drive slot.
Recommandé
AI Accelerator Sled to Host Fabric
The M88RT61632 connects AI accelerator sleds (training accelerators, inference FPGAs, custom ASICs) to the host CPU fabric across sled-to-sled cables and backplane channels. Each sled exposes one or more x16 PCIe 6.x links, and the retimer conditions these signals across the cable/connector boundary where native PCIe 6.x reach would otherwise fail. The chip's >40 dB link budget supports both copper cable and passive backplane channels. Hyperscale designers place a retimer on each sled's host-edge x16 interface to deliver full 64 GT/s PAM4 throughput per lane with FLIT-mode framing and FEC compliance.
Recommandé
Cloud Server PCIe 6.x Riser Card
The M88RT61632 conditions signals on PCIe 6.x riser cards used in 1U and 2U cloud servers where vertical routing distance and connector loss exceed native PCIe 6.x channel budgets. Riser cards typically carry one or two x16 links between the baseboard and add-in cards (NICs, DPUs, accelerators), and the retimer's 16-lane capacity handles both. With >40 dB link budget and low-latency retransmission, the chip preserves PCIe 6.x compliance end-to-end. Cloud-server system designers embed one M88RT61632 on each riser card to deliver full 64 GT/s bandwidth to add-in cards without chassis redesign.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour M88RT61632 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | M88RT51632 |
|---|---|---|
| Brand | Montage Technology | Montage Technology |
| Package | BGA (mainstream industry) | BGA (mainstream industry) |
| PCIe Compliance | PCIe 6.x | PCIe 5.0 |
| CXL Compliance | CXL 3.x | CXL 2.0 |
| Max Data Rate per Lane | 64 GT/s PAM4 | 32 GT/s NRZ |
| Number of Lanes | 16 | 16 |
| Generation | 3rd generation retimer | 2nd generation retimer |
| Status | Sampling (Jan 2025) | Production |
Principaux différenciateurs
- PCIe 6.x / CXL 3.x support with PAM4 64 GT/s (vs M88RT51632)
- Link budget above 40 dB (vs M88RT51632)
- 3rd-generation retimer architecture (vs M88RT51632)
Notes de conception
Follow Montage Technology's reference layout guide for the BGA ball map, SerDes routing, and power-rail decoupling. Use low-impedance supply planes for analog and digital rails, and provide isolated grounds with stitching vias near the SerDes ball array. Maintain 85-ohm differential impedance for PCIe 6.x lanes and keep via stubs minimal to preserve the >40 dB link budget.
The M88RT61632 consumes significant power at 64 GT/s PAM4 across 16 active lanes. Provide adequate copper thermal relief beneath the BGA, and consider airflow across the chip in 1U/2U chassis. Estimated: at full 16-lane 64 GT/s load, expect several watts of dissipation; consult the full Montage datasheet for the exact thermal design power (TDP) figure once released.
PCIe 6.x PAM4 signaling at 64 GT/s is far more sensitive to channel loss than PCIe 5.0 NRZ. Use low-loss PCB materials (e.g., Megtron 6 or equivalent) for long SerDes routes, and place the M88RT61632 as close as practical to the channel break-point. Verify FLIT-mode framing and FEC operation by checking the link-training state machine during system bring-up.
Do not assume the M88RT61632 and M88RT51632 are interchangeable — they target different PCIe/CXL generations (6.x/3.x vs 5.0/2.0) with different signaling rates (PAM4 64 GT/s vs NRZ 32 GT/s). PCB layouts, firmware, and reference designs are not directly portable. Always confirm firmware is loaded via the host management interface before attempting link training.
Informations de conformité
RoHS/REACH status not specified in the verified product brief or product page; full compliance data requires the full datasheet from Montage Technology under NDA. AEC-Q100 not applicable — this is a server / cloud-computing retimer, not an automotive-grade component.
