PC16550D - UART with 16-Byte FIFOs | Texas Instruments
Référence : PC16550D ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $8.95 | $8,95 |
| 10 | $8.2 | $82,00 |
| 100 | $7.45 | $745,00 |
| 500 | $6.9 | $3 450,00 |
| 1 000 | $6.35 | $6 350,00 |
PC16550D Présentation
A UART (Universal Asynchronous Receiver/Transmitter) is a serial communication IC that converts parallel data from a processor bus into asynchronous serial data streams, and back. It sits within the broader hierarchy of interface ICs under the serial communication device class, alongside synchronous counterparts such as USARTs and SPI interfaces. UARTs handle framing, start/stop bit generation, parity checking, and baud-rate generation without a shared clock between endpoints.
The PC16550D is an improved version of the original 16450 UART. On power-up it is functionally identical to the 16450 in CHARACTER mode, and it can also be reset to 16450-mode behavior under software control, ensuring backward compatibility with legacy PC and embedded BIOS software. Entering FIFO mode enables the 16-byte buffers on both the transmit and receive paths, dramatically reducing CPU interrupt load compared with the 16450's single-character holding registers.
Technical depth: the device includes a programmable baud-rate generator, a modem-control block (DTR, DSR, RTS, CTS, DCD, RI), full line-status reporting, and independently controllable transmit and receive FIFO triggers via its FIFO Control Register (FCR). The RXRDY and TXRDY DMA-handshake signals allow direct memory access transfers, further offloading the host processor in high-throughput serial links.
Typical applications include legacy ISA/PCI-era PC COM ports, industrial automation equipment with RS-232/RS-485 links, terminal servers and console-management systems, and embedded processors that need an external memory-mapped UART with modem control.
Design consideration: because PC16550D and PC16552D are discontinued by TI, new designs should evaluate the pin/function-compatible TL16C550 family, which TI explicitly discusses as a replacement path in its support forums; verify FIFO trigger behavior and maximum baud rate against the target application.
This page synthesizes distributor availability data, the TI/National Semiconductor datasheet, and drop-in replacement analysis not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour PC16550D — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
PC16550DN
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
PC16550DIN
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
PC16550CFN
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
TL16C550CJ
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
PC16550D Spécifications
| Fonction | Universal Asynchronous Receiver/Transmitter (UART) |
| UART Channels | 1 |
| FIFO Size (TX) | 16 byte |
| FIFO Size (RX) | 16 byte |
| Compatibility | Upward-compatible with 16450 (CHARACTER mode at power-up) |
| Operating Mode | CHARACTER mode (16450-compatible) and FIFO mode (software selectable) |
| Modem Control Signals | DTR, DSR, RTS, CTS, DCD, RI |
| DMA Support | RXRDY and TXRDY handshake signals |
| Baud Rate Generator | Programmable, on-chip |
| Boîtier | 40-pin DIP (PC16550DN) |
| Type de montage | Through-Hole |
| Interrupt Output | INTR, programmable via IER |
| Statut du cycle de vie | Discontinued (per TI E2E forum); PC16550DN listed active at DigiKey |
Guide de configuration des broches du PC16550D 40-pin dip (pc16550dn)
Configuration des broches du PC16550D (boîtier 40-pin dip (pc16550dn)). La numérotation des broches, les fonctions et les schémas de connexion sont définis dans la fiche technique du fabricant. Consultez-la pour l'empreinte exacte et les directives de soudage.
Aucune donnée de brochage détaillée disponible pour PC16550D.
Consultez la fiche technique pour la configuration complète des broches.
Applications typiques
PC16550D convient pour 6 applications: Legacy PC COM Ports, Industrial RS-485 / RS-232 Networks, Console and Terminal Servers, Embedded Processors Needing a Hardware UART, Retrofit and Legacy Equipment Maintenance, Point-of-Sale and Peripheral Interfacing.
Legacy PC COM Ports
The PC16550D was the de-facto standard UART for IBM PC-compatible COM ports through the ISA era. Its power-up compatibility with the 16450 in CHARACTER mode means PC BIOS and DOS-era drivers operate without modification, while enabling FIFO mode unlocks the 16-byte buffers for higher-throughput modem and serial links. The on-chip programmable baud generator derives standard PC baud rates from the 1.8432 MHz clock, and the full modem-control block (DTR, DSR, RTS, CTS, DCD, RI) supports dial-up modem handshaking. RXRDY/TXRDY signals permit ISA DMA transfers, offloading the CPU during large file transfers.
Recommandé
Industrial RS-485 / RS-232 Networks
In factory automation and building-control equipment, the PC16550D provides the asynchronous serial engine behind RS-232 line drivers or RS-485 transceivers. The 16-byte FIFOs smooth burst traffic from PLCs and field devices, while the RTS modem-control output can gate RS-485 driver-enable with software-controlled turnaround timing. The programmable baud generator covers standard industrial rates, and the line-status register exposes overrun, parity, and framing errors for robust error handling. RXRDY/TXRDY DMA handshake reduces interrupt jitter on deterministic polling loops in multi-drop networks.
Recommandé
Console and Terminal Servers
Console-management and terminal-server products aggregate many serial ports for out-of-band administration of servers and network switches. A PC16550D per port gives each channel independent 16-byte FIFOs, a full modem-control set, and the industry-standard 16550 register interface that mature multi-port drivers target directly. FIFO mode minimizes per-character interrupt load across dozens of concurrent channels, and the DMA handshake supports high-aggregate throughput. The software-selectable 16450 compatibility mode aids bring-up and legacy diagnostics before enabling FIFO operation in production firmware.
Recommandé
Embedded Processors Needing a Hardware UART
Microcontrollers and DSP systems without a spare hardware UART, or lacking modem-control signals, can memory-map a PC16550D onto the external bus. The device decodes chip selects (CS0-CS2) with an ADS address-strobe option for multiplexed buses, and its 8-bit data bus connects directly to standard 8/16-bit host interfaces. The INTR output ties to the MCU interrupt controller, while RXRDY/TXRDY feed DMA controllers for low-latency streaming. Software-selectable FIFO trigger levels let firmware balance interrupt latency against throughput for the specific application.
Recommandé
Retrofit and Legacy Equipment Maintenance
Service organizations maintaining avionics test sets, medical instrumentation, and process-control gear built around the 16550 need exact-form-factor replacements. The PC16550DN retains the 40-pin DIP through-hole package and 16450 power-up compatibility, letting existing boards and firmware run unchanged. Where the bare PC16550D marking is unavailable, the pin-compatible TL16C550CJ in 40-DIP is the TI-discussed successor, requiring only datasheet-level verification of FIFO trigger timing. Sourcing through residual distributor stock keeps legacy fleets alive without PCB redesign or driver recertification.
Recommandé
Point-of-Sale and Peripheral Interfacing
Receipt printers, barcode scanners, card readers, and cash drawers historically communicate over RS-232 serial links driven by a 16550-class UART. The PC16550D's modem-control lines implement the busy/ready handshaking many POS peripherals expect, and its FIFOs absorb printer burst data without host stalls. The programmable baud generator covers the legacy rates (9600 to 115.2 kbps) common in retail hardware, and the line-status register lets POS firmware detect cable faults via framing-error monitoring, improving transaction reliability in electrically noisy retail environments.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour PC16550D — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | PC16550DN | PC16550DIN | PC16550CFN | TL16C550CJ |
|---|---|---|---|---|---|
| Package | 40-pin DIP | 40-pin DIP - same | 40-pin DIP - same | 40-pin DIP - same | 40-pin DIP - same |
| Brand | Texas Instruments (National Semiconductor heritage) | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| UART Channels | 1 | 1 | 1 | 1 | 1 |
| FIFO Size | 16 byte TX / 16 byte RX | 16 byte | 16 byte | 16 byte | 16 byte |
| 16450 Compatibility Mode | Yes (CHARACTER mode at power-up) | Yes | Yes | Yes | Yes |
| DMA Handshake (RXRDY/TXRDY) | Yes | Yes | Yes | Yes | Yes |
| Lifecycle Status | Discontinued (residual stock possible) | Listed active at DigiKey (residual) | Discontinued | Discontinued | Active (recommended for new designs) |
Principaux différenciateurs
- Software-selectable 16450 compatibility mode (vs TL16C550CJ)
- Active distributor availability of the DN suffix (vs PC16550DIN)
- Legacy PC-standard register interface (vs TL16C750)
Notes de conception
The single most important design decision with the PC16550D today is sourcing, not electronics: TI confirms on its E2E forum that PC16550D and PC16552D are discontinued. For any new production build, qualify the active TL16C550C family instead, and verify the exact package suffix for footprint compatibility. For legacy repairs, buy PC16550DN from authorized distributors while residual stock lasts, and be wary of remarked parts from unverified brokers when buying date-code-sensitive obsolete silicon.
As a 40-pin DIP through-hole device, the PC16550D needs no thermal copper, but layout still matters for signal integrity on the serial lines. Place the RS-232 transceiver (e.g., MAX232) close to the SIN/SOUT pins, keep the modem-control ribbon stubs short, and decouple VCC with a 100 nF ceramic capacitor directly at pin 40 to VSS. If you derive RS-485 driver-enable from RTS, route RTS to the transceiver DE pin without crossing the clock lines to minimize turnaround glitch risk.
Confirm the supply-voltage and operating-temperature ratings in the TI datasheet for your exact suffix (commercial vs industrial: DN vs DIN) before finalizing the power budget - these values are not reproduced on this page and must not be assumed. Because CMOS UART idle current is small, system power impact is negligible, but legacy 5V-only operation means level shifting is mandatory when interfacing to 3.3V MCUs; use a level translator on the 8-bit data and control bus rather than relying on marginal logic thresholds.
Informations de conformité
Compliance data was not present in the provided web data. As a legacy National Semiconductor-era part, older date codes are unlikely to be RoHS/lead-free compliant; verify per date code with the supplier.
