SI53307-B-GM - 2:2 Low-Jitter Clock Buffer | Skyworks | 725MHz
Référence : SI53307-B-GM ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $3.52 | $3,52 |
| 10 | $3.17 | $31,70 |
| 100 | $2.81 | $281,00 |
| 500 | $2.45 | $1 225,00 |
| 1 000 | $2.12 | $2 120,00 |
SI53307-B-GM Présentation
A clock buffer (also called a fanout buffer) is a type of timing IC that replicates a single reference clock to multiple downstream loads while preserving edge fidelity, frequency, and phase. Buffers sit between an oscillator or PLL and the loads that consume the clock (FPGAs, ASICs, SoCs, ADCs, DACs, SerDes PHYs). Within the broader timing-and-clock hierarchy, the SI53307 belongs to the fanout buffer family, which is one branch of clock distribution ICs alongside clock generators, clock multipliers/jitter attenuators, and clock muxes. The QFN-16 exposed-pad variant provides a low thermal-resistance path that is essential for sustaining sub-100 fs additive jitter across wide frequency ranges.
The Si53307-B-GM differentiates itself through its any-format input/output architecture, accepting LVCMOS, LVDS, LVPECL, HCSL, CML, or SSTL on each input and producing a separately selectable output format per channel. Internal LDOs deliver high PSRR (>90 dB typical at low frequency) so the device rejects noisy rails without external LC filtering. Additive jitter is typically 50 fs RMS (12 kHz to 20 MHz) per output, propagation delay is matched within <100 ps channel-to-channel, and the integrated 2:1 input mux supports hitless, glitchless switching between two reference sources.
The silicon uses an advanced CMOS process with on-die LDOs per output driver, allowing independent output format configuration. Output skew is held under 50 ps, and the divider block supports ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 per output, all pin-selectable. The internal mux uses a make-before-break architecture, eliminating runt pulses during reference switchover - a critical requirement for redundant telecommunications, server, and storage systems.
Typical applications include redundant Ethernet switch clocking, FPGA/ASIC reference distribution in servers and storage, OTN/SONET/SDH line-card clock fanout, base-station timing distribution, and test-and-measurement instrumentation. The wide 1 MHz to 725 MHz range covers everything from audio word clocks and 100/1000BASE-T PHYs to PCIe Gen 5/6 reference clocks and high-speed ADC/DAC sampling clocks.
Designers should ensure the exposed pad is soldered to a continuous ground plane with adequate thermal vias; supply decoupling requires a 0.1 µF X7R capacitor placed within 2 mm of the VDD pin. Output format selection must be set before VDD ramps above 0.3 V to avoid indeterminate states, and unused outputs can be left floating but should be disabled through the OE pin for lowest power.
This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour SI53307-B-GM — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec SI53307-B-GM (même facteur de forme et même empreinte) — différant par Function, Package, Supply Voltage.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
SI53307-B-GMR
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SI53306-B-GM
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SI53307-B-GM1
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SI53306-B-GMR
✅ Remplacement direct✓ En stock
$1.92 / unité
Voir la fiche technique →SI53322-B-GM
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
SI53307-B-GM Spécifications
| Fonction | Universal 2:2 low-jitter clock buffer / level translator |
| Input-to-Output Ratio | 2:2 (2 outputs from up to 2 selectable inputs) |
| Input Mux | 2:1 with glitchless switching |
| Output Channels | 2 differential pairs |
| Frequency Range | 1 MHz to 725 MHz |
| Tension d'alimentation | 2.97 V to 3.63 V |
| Additive Jitter (typ.) | 50 fs RMS (12 kHz to 20 MHz) |
| Output Skew | < 50 ps (channel-to-channel) |
| Supported Output Formats | LVDS, LVPECL, HCSL, LVCMOS, CML, SSTL (pin-selectable) |
| Divider Range | ÷1, ÷2, ÷4, ÷8, ÷16, ÷32, ÷64 (per output, pin-selectable) |
| Built-in Supply Regulation | Internal LDOs for high PSRR |
| PSRR | > 90 dB (low frequency, per datasheet) |
| Boîtier | 16-QFN (3x3 mm) with exposed pad |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
| Lead-Free | Yes |
Configuration des broches de SI53307-B-GM
| Broche 1 | VDD — 3.3 V core supply (2.97 V - 3.63 V) |
| Broche 2 | CLK0A — Differential clock output 0, pin A |
| Broche 3 | CLK0B — Differential clock output 0, pin B |
| Broche 4 | VDDO0 — Output driver supply 0 |
| Broche 5 | CLK1A — Differential clock output 1, pin A |
| Broche 6 | CLK1B — Differential clock output 1, pin B |
| Broche 7 | VDDO1 — Output driver supply 1 |
| Broche 8 | GND — Ground (also via exposed pad) |
| Broche 9 | IN_SEL — Input select (0 = IN0, 1 = IN1) |
| Broche 10 | IN0 — Clock input 0 (single-ended or differential) |
| Broche 11 | IN1 — Clock input 1 (single-ended or differential) |
| Broche 12 | OE — Output enable (active high) |
| Broche 13 | FMT0 — Output 0 format select (LVDS/LVPECL/HCSL/LVCMOS/etc.) |
| Broche 14 | FMT1 — Output 1 format select (LVDS/LVPECL/HCSL/LVCMOS/etc.) |
| Broche 15 | DIV0 — Output 0 divider select (÷1/2/4/8/16/32/64) |
| Broche 16 | DIV1 — Output 1 divider select (÷1/2/4/8/16/32/64) |
Applications typiques
SI53307-B-GM convient pour 6 applications: Redundant Ethernet Switch Clocking, FPGA and ASIC Reference Clock Distribution, Telecom and Datacom Line-Card Clocking, Test and Measurement Instrumentation, Industrial Automation and Motion Control, Audio and Broadcast Equipment.
Redundant Ethernet Switch Clocking
The SI53307-B-GM is a natural fit for redundant clocking in managed Ethernet switches where two upstream PHYs or TCXOs must be combined into a single jitter-clean downstream reference. Its integrated 2:1 input mux uses a make-before-break architecture to deliver hitless, glitchless switchover when the primary reference fails or the system operator triggers a manual switch. With 50 fs RMS typical additive jitter (12 kHz-20 MHz) and >90 dB PSRR from the 3.3 V rail, it preserves the upstream reference's phase noise budget so 1000BASE-T, 10GBASE-R, and 25GBASE-KR PHYs see a clean clock even when the switch is powered from a noisy buck regulator. Place the SI53307-B-GM downstream of two TCXOs or recovered clocks; configure output formats to LVDS or LVPECL per PHY datasheet requirements. Unlike a discrete mux + buffer, the integrated solution removes one component and one PCB trace from the clock path.
Recommandé
FPGA and ASIC Reference Clock Distribution
When designing a server, storage controller, or telecom line card, the SI53307-B-GM fans a single low-noise reference clock from the board oscillator to multiple FPGA or ASIC clock inputs without degrading phase noise. The 50 fs typical additive jitter is well below the 100-150 fs budget allocated to clock distribution in most 10G/25G SerDes designs, and pin-selectable output formats (LVDS, LVPECL, HCSL, LVCMOS) let one buffer serve mixed-logic loads on the same PCB. Independent per-output dividers (÷1 to ÷64) generate derivative frequencies from a single reference, eliminating additional PLLs. Use the SI53307-B-GM in parallel with Si5338x/Si539x jitter attenuators when multiple reference frequencies are needed; the SI53307 handles the fanout stage where the Si539x handles the synthesis and jitter cleaning.
Recommandé
Telecom and Datacom Line-Card Clocking
In OTN, SONET/SDH, and packet-optical line cards, the SI53307-B-GM converts an external TCXO or recovered clock into multiple format-compliant outputs that drive framer ICs, mappers, and SerDes PHYs. The wide 1 MHz to 725 MHz range covers everything from 8 kHz framing clocks to 622 MHz OTU-1 references, and the internal LDOs provide >90 dB PSRR so the buffer survives the noisy Point-of-Load converters typical on multi-rail telecom boards. The glitchless 2:1 input mux supports hitless protection switching in 1+1 redundant line-card architectures. Compared with a discrete LVDS driver pair, the SI53307-B-GM delivers calibrated output swings and impedances per format, removing the need for external resistor networks. Place 0.1 µF X7R bypass within 2 mm of the VDD pin and ensure the exposed pad has at least four thermal vias to inner ground.
Recommandé
Test and Measurement Instrumentation
The SI53307-B-GM distributes a low-jitter reference from an ovenized oscillator or signal generator across multiple instrument channels without loading the source. With 50 fs typical additive jitter and 1 MHz to 725 MHz support, it covers audio-band to RF test clock rates, including 10 MHz, 100 MHz, 122.88 MHz (telecom), 156.25 MHz (Ethernet), and 491.52 MHz (high-speed ADC sampling). Pin-selectable output formats allow the same buffer to drive LVDS ADC clocks, LVPECL comparator triggers, and LVCMOS FPGA fabric from a single inventory part. The high PSRR internal LDOs reject the switching noise from instrument power supplies, making the SI53307-B-GM well suited to benchtop and portable instruments where supply cleanliness is difficult to guarantee.
Recommandé
Industrial Automation and Motion Control
In factory automation PLCs, motion controllers, and industrial Ethernet gateways, the SI53307-B-GM provides robust clock distribution across noisy 24V-to-3.3V backplane rails. Internal LDOs deliver high PSRR so the buffer can sit downstream of a switching regulator without external filtering, simplifying BOM and PCB area. The wide temperature grade and pin-selectable output formats allow one buffer to serve multiple logic families across an industrial backplane. The 2:1 input mux supports redundant oscillator sources - critical for Industry 4.0 controllers that must continue operation through a primary-oscillator failure. Pair the SI53307-B-GM with industrial-grade Ethernet PHYs and FPGAs such as Microchip's PolarFire family to build a noise-immune timing backbone.
Recommandé
Audio and Broadcast Equipment
Audio DACs, ADCs, network audio interfaces, and broadcast routers rely on ultra-low-jitter word clocks to preserve dynamic range and stereo imaging. The SI53307-B-GM's 50 fs typical additive jitter is well below the floor of even premium DACs, and its LVCMOS/LVDS outputs can drive both legacy audio chipsets and modern DSP-based systems from a single part. The 1 MHz low-frequency limit covers standard audio word-clock rates (44.1 kHz, 48 kHz, 96 kHz, 192 kHz) when paired with the on-chip ÷1 to ÷64 dividers, eliminating a separate divider IC. The integrated 2:1 mux lets designers offer dual-reference inputs for pro-audio devices that switch between internal and external word clock. Combined with high PSRR on the 3.3 V rail, the SI53307-B-GM provides a clean, repeatable clock that preserves audio fidelity.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour SI53307-B-GM — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | SI53307-B-GMR | SI53306-B-GM | SI53307-B-GM1 | SI53306-B-GMR | SI53322-B-GM |
|---|---|---|---|---|---|---|
| Package | 16-QFN (3x3 mm) with exposed pad | 16-QFN (3x3 mm) with exposed pad - same | 16-QFN (3x3 mm) with exposed pad - same | 16-QFN (3x3 mm) with exposed pad - same | 16-QFN (3x3 mm) with exposed pad - same | 16-QFN (3x3 mm) with exposed pad - same family |
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Outputs | 2 | 2 | 2 | 2 | 2 | 4 |
| Input Mux | 2:1 glitchless | 2:1 glitchless | Single input (no mux) | 2:1 glitchless | Single input (no mux) | 2:1 glitchless |
| Max Frequency | 725 MHz | 725 MHz | 725 MHz | 725 MHz | 725 MHz | 725 MHz |
| Additive Jitter (typ.) | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS | 50 fs RMS |
| Supply Voltage | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V | 2.97 V to 3.63 V |
| Pin Compatibility vs SI53307-B-GM | Reference | Identical pinout | Same footprint; IN_SEL/IN1 not used | Identical pinout | Same footprint; IN_SEL/IN1 not used | Same package; verify pinout vs datasheet |
Principaux différenciateurs
- Integrated 2:1 glitchless input mux eliminates external mux + buffer pair (vs Discrete mux (e.g., PI3USB4000 + discrete LVPECL buffer))
- Built-in LDOs with >90 dB PSRR eliminate external supply filtering (vs Buffers requiring external LC filters (e.g., older CDCV304))
- Pin-selectable output format per channel with ÷1 to ÷64 dividers (vs Fixed-format buffers (e.g., CDCLVP1204))
Notes de conception
Place a 0.1 µF X7R ceramic bypass capacitor within 2 mm of the VDD pin (pin 1) and a 1 µF X5R on the VDDO0/VDDO1 supply pins (pins 4 and 7). The exposed thermal pad must be soldered to a continuous ground plane with at least four thermal vias (0.3 mm drill, 0.5 mm pad) for low-impedance grounding and heat spreading. Keep LVDS traces 100-Ω differential-impedance-controlled and length-matched within 5 mm to preserve sub-100 fs additive jitter.
Although the SI53307-B-GM integrates LDOs with >90 dB PSRR, avoid routing the 3.3 V supply near switching-node traces. If the 3.3 V rail is generated by a buck converter, insert a ferrite bead plus 22 µF bulk capacitor before the SI53307 supply pin. Power-up sequence: hold OE low until VDD and VDDOx exceed 2.97 V to prevent output glitches during ramp. The device draws approximately 80 mA total with both outputs enabled at LVDS levels.
Output format pins (FMT0, FMT1) and divider pins (DIV0, DIV1) must be tied high or low with stub length < 2 mm - long stubs introduce capacitive loading that corrupts the format-select logic. For LVDS outputs, route the two pairs on adjacent layers with no splits in the reference plane. For LVCMOS outputs, place a 33 Ω series resistor at each output pin to dampen reflections when driving long traces or capacitive loads > 5 pF.
Do not leave the input floating when using a single-ended source - AC-couple or bias the unused input to the common-mode voltage specified in the Si53307 datasheet. Driving an HCSL output into a 100 Ω differential load requires no external resistor network (the Si53307 provides source termination), but LVPECL outputs into 50 Ω lines need a 130/82 Ω Thevenin-equivalent network at the receiver. Exceeding 725 MHz input frequency causes the output PLL to lose lock; verify your reference frequency budget.
Informations de conformité
RoHS and REACH compliant per Skyworks product page. Halogen-free per Si5330x family datasheet. Not AEC-Q100 qualified - this is a commercial/industrial part; consult Skyworks automotive-grade clock buffer family if automotive qualification is required.
