STM32F405RGT7TR - 168MHz Cortex-M4 MCU, 1MB Flash | STMicroelectronics
Référence : STM32F405RGT7TR ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $11.51 | $11,51 |
| 10 | $10.36 | $103,60 |
| 100 | $9.21 | $921,00 |
| 500 | $8.34 | $4 170,00 |
| 1 000 | $7.62 | $7 620,00 |
STM32F405RGT7TR Présentation
What is a Cortex-M4 microcontroller? A microcontroller (MCU) is a single-chip computer that integrates a CPU core, memory, and peripherals. The Cortex-M4 is Arm's mainstream mixed-signal MCU core, adding hardware FPU and DSP extensions on top of the Cortex-M3 architecture, targeted at applications that demand both deterministic control and real-time signal processing. In the taxonomy chain: Cortex-M4 -> ARM Cortex-M -> 32-bit RISC MCU -> microcontroller -> embedded semiconductor.
Key features include three 12-bit ADCs (2.4 MSPS), two 12-bit DACs, USB 2.0 OTG full-speed and high-speed with on-chip PHY, 10/100 Ethernet MAC, two CAN 2.0B interfaces, an SDIO for SD/MMC cards, and 17 timers plus three I2C, four USART/UART, three SPI, and two I2S peripherals. The integrated 4-byte CCM data SRAM is useful for packet storage in Ethernet stacks, while the FSMC memory controller allows external SRAM, NOR/NAND Flash, and PSRAM expansion. Operating voltage spans 1.8 V to 3.6 V.
The architecture uses a multi-layer AHB/APB bus matrix with seven peripheral DMA channels supporting parallel data streams without CPU intervention. The ART Accelerator with 64-bit Flash interface and prefetch buffer delivers true 0-wait-state execution even at 168 MHz. Cryptographic options include AES 128/192/256-bit hardware acceleration on STM32F407 family SKUs; the F405 is the non-crypto variant. Low-power modes (Sleep, Stop, Standby) plus a VBAT domain for RTC and backup registers suit battery-backed designs.
Typical applications include industrial motor drives (FOC control via DSP), USB peripherals and HID devices, Ethernet-connected IoT gateways, audio processing with I2S/SAI interfaces, and high-speed data acquisition with triple interleaved ADCs. Developers use STM32CubeIDE, STM32CubeMX, and the HAL/LL driver libraries for code generation and bring-up.
When designing with this MCU, pay close attention to power-rail decoupling (1 uF + 100 nF near each VDD pin, plus a 4.7 uF bulk), BOOT0 strap configuration, and JTAG/SWD header placement for in-system programming. The 64-pin LQFP footprint leaves generous board space for crystal, reset, and decoupling networks while exposing most peripherals.
This page synthesizes distributor pricing, same-family STM32 drop-in alternatives, design considerations from the manufacturer reference manual, and FAQ content not aggregated on a single distributor page.
Alternatives de remplacement direct pour STM32F405RGT7TR — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
Aucune alternative de remplacement direct disponible pour ce produit.
Demander des alternativesSTM32F405RGT7TR Valeurs maximales et caractéristiques électriques
| Core Architecture | Arm Cortex-M4F (32-bit RISC with FPU and DSP) |
| Fréquence d'horloge maximale | 168 MHz |
| DMIPS Performance | 210 DMIPS (1.25 DMIPS/MHz, Dhrystone 2.1) |
| Program Flash Memory | 1 Mbyte (with ART Accelerator, 0-wait-state execution) |
| SRAM | 192 Kbytes main SRAM + 4 Kbytes CCM data SRAM |
| Tension d'alimentation | 1.8 V to 3.6 V |
| Plage de température de fonctionnement | -40 C to +105 C (grade 7) |
| Boîtier | LQFP-64 (10x10 mm, 0.5 mm pitch) |
| GPIO Count | 51 (multiplexed with peripherals) |
| ADC | 3 x 12-bit, 2.4 MSPS, up to 24 channels |
| DAC | 2 x 12-bit |
| USB | USB 2.0 OTG FS + USB 2.0 OTG HS with on-chip PHY |
| Ethernet | 10/100 MAC (IEEE 1588 PTP support); external PHY required |
| CAN | 2 x CAN 2.0B active |
| Timers | 17 (including 1 SysTick, 2 watchdog, 1 RTC) |
| Communication Peripherals | 3 x SPI, 3 x I2C, 4 x USART/UART, 2 x I2S, 1 x SDIO, 1 x FSMC |
| DMA Controllers | 2 x 8-stream DMA (16 streams total) |
| Type de montage | Surface Mount |
| Niveau MSL | MSL3 (per JEDEC J-STD-020) |
| Statut RoHS | Compliant |
Configuration des broches de STM32F405RGT7TR
| Broche 1 | PE2 — General-purpose I/O PE2, TRACECLK, FSMC_A23 |
| Broche 2 | PE3 — General-purpose I/O PE3, TRACED0, FSMC_A19 |
| Broche 3 | PE4 — General-purpose I/O PE4, TRACED1, FSMC_A20 |
| Broche 4 | PE5 — General-purpose I/O PE5, TRACED2, FSMC_A21 |
| Broche 5 | PE6 — General-purpose I/O PE6, TRACED3, FSMC_A22 |
| Broche 6 | VBAT — Backup battery supply for RTC and backup registers |
| Broche 7 | PC13 — GPIO PC13, RTC_TAMP1, RTC_OUT - special anti-tamper function |
| Broche 8 | PC14/OSC32_IN — GPIO PC14 / 32.768 kHz LSE oscillator input |
| Broche 9 | PC15/OSC32_OUT — GPIO PC15 / 32.768 kHz LSE oscillator output |
| Broche 10 | OSC_IN — HSE crystal oscillator input (8-25 MHz) |
| Broche 11 | OSC_OUT — HSE crystal oscillator output |
| Broche 12 | NRST — Active-low reset input; can be left open if external reset not needed |
| Broche 13 | VREF+ — ADC reference voltage (tie to VDDA) |
| Broche 14 | VREF- — ADC reference ground (tie to VSSA) |
| Broche 15 | VDDA — Analog supply voltage (1.8-3.6 V); requires decoupling network |
| Broche 16 | PA0/WKUP — GPIO PA0, WKUP1 from Standby, ADC1_IN0, TIM2_CH1 |
| Broche 17 | PA1 — GPIO PA1, ADC1_IN1, TIM2_CH2 |
| Broche 18 | PA2 — GPIO PA2, USART2_TX, ADC1_IN2, TIM5_CH3 |
| Broche 19 | PA3 — GPIO PA3, USART2_RX, ADC1_IN3, TIM5_CH4 |
| Broche 20 | VSS_4 — Digital ground |
| Broche 21 | VDD_4 — Digital supply (1.8-3.6 V); decoupling required |
| Broche 22 | PA4 — GPIO PA4, SPI1_NSS, USART2_CK, ADC1_IN4, DAC1_OUT |
| Broche 23 | PA5 — GPIO PA5, SPI1_SCK, ADC1_IN5, DAC2_OUT |
| Broche 24 | PA6 — GPIO PA6, SPI1_MISO, ADC1_IN6, TIM13_CH1 |
| Broche 25 | PA7 — GPIO PA7, SPI1_MOSI, ADC1_IN7, TIM14_CH1 |
| Broche 26 | PB0 — GPIO PB0, ADC1_IN8, TIM3_CH3 |
| Broche 27 | PB1 — GPIO PB1, ADC1_IN9, TIM3_CH4 |
| Broche 28 | PB2/BOOT1 — GPIO PB2 / boot mode select 1 |
| Broche 29 | PB10 — GPIO PB10, USART3_TX, I2C2_SCL, TIM2_CH3 |
| Broche 30 | PB11 — GPIO PB11, USART3_RX, I2C2_SDA, TIM2_CH4 |
| Broche 31 | VSS_1 — Digital ground |
| Broche 32 | VDD_1 — Digital supply (1.8-3.6 V); decoupling required |
| Broche 33 | PB12 — GPIO PB12, SPI2_NSS, I2S2_WS, CAN2_RX, TIM1_BKIN |
| Broche 34 | PB13 — GPIO PB13, SPI2_SCK, I2S2_CK, CAN2_TX, TIM1_CH1N |
| Broche 35 | PB14 — GPIO PB14, SPI2_MISO, TIM1_CH2N |
| Broche 36 | PB15 — GPIO PB15, SPI2_MOSI, TIM1_CH3N |
| Broche 37 | PC6 — GPIO PC6, USART6_TX, TIM3_CH1, FSMC_NWAIT |
| Broche 38 | PC7 — GPIO PC7, USART6_RX, TIM3_CH2, FSMC_NE1 |
| Broche 39 | PC8 — GPIO PC8, TIM3_CH3, USART6_CK, FSMC_NE2 |
| Broche 40 | PC9 — GPIO PC9, TIM3_CH4, I2C3_SDA, FSMC_NE3 |
| Broche 41 | PA8 — GPIO PA8, USART1_CK, TIM1_CH1, MCO1, USB_FS_SOF |
| Broche 42 | PA9 — GPIO PA9, USART1_TX, TIM1_CH2, USB_VBUS_FS |
| Broche 43 | PA10 — GPIO PA10, USART1_RX, TIM1_CH3, OTG_FS_ID |
| Broche 44 | PA11 — GPIO PA11, CAN1_RX, TIM1_CH4, OTG_FS_DM |
| Broche 45 | PA12 — GPIO PA12, CAN1_TX, TIM1_ETR, OTG_FS_DP |
| Broche 46 | PA13 — GPIO PA13, JTMS, SWDIO |
| Broche 47 | VSS_2 — Digital ground |
| Broche 48 | VDD_2 — Digital supply (1.8-3.6 V); decoupling required |
| Broche 49 | PA14 — GPIO PA14, JTCK, SWCLK |
| Broche 50 | PA15 — GPIO PA15, JTDI, SPI3_NSS, I2S3_WS, TIM2_CH1 |
| Broche 51 | PC10 — GPIO PC10, USART3_TX, I2C3_SCL, FSMC_NE4 |
| Broche 52 | PC11 — GPIO PC11, USART3_RX, I2C3_SDA, FSMC_NCE2 |
| Broche 53 | PC12 — GPIO PC12, USART3_CK, FSMC_NCE3 |
| Broche 54 | PD2 — GPIO PD2, TIM3_ETR, USART3_RTS |
| Broche 55 | PB3 — GPIO PB3, JTDO, SPI3_SCK, I2S3_CK, TIM2_CH2 |
| Broche 56 | PB4 — GPIO PB4, NJTRST, SPI3_MISO, TIM3_CH1 |
| Broche 57 | PB5 — GPIO PB5, I2C1_SMBAI, SPI3_MOSI, I2S3_SD, TIM3_CH2 |
| Broche 58 | PB6 — GPIO PB6, I2C1_SCL, USART1_TX, TIM4_CH1 |
| Broche 59 | PB7 — GPIO PB7, I2C1_SDA, USART1_RX, TIM4_CH2 |
| Broche 60 | BOOT0 — Boot mode select 0; controls bootloader/main-Flash selection at reset |
| Broche 61 | PB8 — GPIO PB8, I2C1_SCL, CAN1_RX, TIM4_CH3, SDIO_D5 |
| Broche 62 | PB9 — GPIO PB9, I2C1_SDA, CAN1_TX, TIM4_CH4, SDIO_D6 |
| Broche 63 | VSS_3 — Digital ground |
| Broche 64 | VDD_3 — Digital supply (1.8-3.6 V); decoupling required |
Applications typiques
STM32F405RGT7TR convient pour 6 applications: Industrial Motor Drive / FOC Control, USB HID / Composite Device, Ethernet IoT Gateway, Audio Processing / I2S Audio Codec Interface, High-Speed Data Acquisition, Industrial / Building Automation Controllers.
Industrial Motor Drive / FOC Control
The STM32F405RGT7TR's 168 MHz Cortex-M4F with single-precision FPU and full DSP instruction set is purpose-built for field-oriented control (FOC) of three-phase BLDC and PMSM motors used in industrial drives, robotics, and CNC spindle control. The hardware FPU runs Park/Clarke transforms and PID loops without software float emulation overhead, achieving sub-1 microsecond current-loop service times at 20 kHz PWM. Three 12-bit 2.4 MSPS ADCs simultaneously sample motor phase currents, DC-bus voltage, and potentiometer feedback with channel-to-channel skew under 50 ns, critical for accurate I-Park demodulation. The 17 timers include two advanced PWM timers (TIM1, TIM8) with complementary outputs and programmable dead-time insertion, supporting center-aligned switching frequencies up to 100 kHz without choking CPU resources. The DMA-driven PWM-DAC synchronization and the integrated USB OTG HS PHY enable real-time firmware tuning over USB without halting the motor, while the large 1 Mbyte Flash allows full motor-library and state-machine firmware on-chip. Reference design: ST's STM32F4 PMSM FOC SDK v5 (single-shunt and three-shunt topologies). Designers can pair the chip with IGBT gate drivers such as STGAP1AQM or with external op-amps like TI LMV358 for current-sensing signal conditioning.
Recommandé
USB HID / Composite Device
The dual USB 2.0 OTG ports (FS + HS with on-chip PHY) on the STM32F405RGT7TR enable integration of both USB peripherals and hosts without an external ULPI transceiver. The integrated high-speed PHY supports 480 Mbps signaling, so streaming applications such as USB audio class 2.0 speakers, USB-to-UART bridges, or USB HID game controllers can be implemented using only the MCU plus ESD protection and a USB-C connector. The 192 Kbyte SRAM is sufficient to host typical USB Class drivers (CDC, HID, Vendor) plus a small USB-PD negotiated VBUS role, while 1 Mbyte Flash accommodates composite-device stacks (MSC + CDC + HID). The DMA-driven serial-interface peripherals (SPI, I2S) share the AHB bus with USB endpoints, allowing simultaneous streaming of high-bandwidth endpoints and audio I2S playback without packet starvation. Compared to cost-down MCUs without USB HS, the on-chip PHY saves BOM cost and PCB area, especially in space-constrained streaming-dongle form factors. Reference design: ST's STM32CubeMX USB OTG Device class library, including CDC, HID, and DFU composite examples.
Recommandé
Ethernet IoT Gateway
The integrated 10/100 Ethernet MAC with IEEE 1588 PTP hardware timestamping on the STM32F405RGT7TR makes the part a compact foundation for low-cost IoT gateways and edge-devices that need deterministic sub-millisecond timing. Pairing the MCU with an external PHY such as the Microchip KSZ8081RNA or the LAN8720A gives a complete MII/RMII Ethernet port; the MAC then runs LwIP, TCP/IP, or uIP stacks. The 4 Kbyte Core-Coupled Memory (CCM SRAM) is ideal for packet buffers because it runs at CPU speed while remaining inaccessible to Ethernet DMA, eliminating contention on the network slowdowns. The CMSIS-RTOS support and 192 Kbyte main SRAM allow a fully featured gateway running an HTTP server, MQTT client, TLS 1.2 via MbedTLS, and process telemetry at 100 ms cadence while sustaining line-rate Ethernet. Compared to older STM32F1 devices without hardware PTP timestamping, the F405 enables synchronization to NTP-wakeup with sub-100 microsecond jitter. Reference design: ST's STM32CubeMX LwIP HTTP server example for Nucleo-F405RG.
Recommandé
Audio Processing / I2S Audio Codec Interface
The two I2S peripherals and SAI (Serial Audio Interface) on the STM32F405RGT7TR provide full-duplex audio with bit-depths up to 32 bits at sample rates well beyond 192 kHz. The 168 MHz Cortex-M4F with single-precision FPU runs real-time biquad filter chains, dynamic range compressors, and FFT-based spectrum displays, sustaining hundreds of operations per stereo frame. The dual DMA stream structure lets audio sample flow into SRAM via DMA while the processor simultaneously outputs processed audio to a DAC, ensuring zero CPU stalls and click-free playback. USB Audio Class 2.0 endpoints over USB HS offer plug-and-play connectivity to PCs and mobile devices, with the 1 Mbyte Flash holding up to 16 Mbyte-equivalent DSP algorithm code in compressed form. The peripheral cross-bar allows I2S frame-sync routed to timers for sub-millisecond lip sync with video. Reference design: ST's UM1865 audio framework plus STM32F4-DISCO board acoustic BSP.
Recommandé
High-Speed Data Acquisition
With three 12-bit ADCs at 2.4 MSPS each and dual-sample-and-hold capability, the STM32F405RGT7TR achieves an aggregate ADC throughput of 7.2 MSPS - more than adequate for 1 MHz-bandwidth oscilloscope-style data acquisition or ultrasonic phased-array front-ends. Interleaving all three ADCs in dual-mode quadruples the effective sample rate to over 7 MSPS for high-bandwidth transient capture. The double-precision FSM (Fast Stream Multiplier) and 64-bit ART Accelerator bus prefetch allow DMA-collected sample streams to land in SRAM, with the DMA zero-overhead path preventing ADC-overrun under sustained conversion load. The 192 Kbyte SRAM provides 49100 16-bit samples of buffer at full ADC rate, sufficient for 5 milliseconds of single-channel scan at 7.2 MSPS or several seconds at lower rates. GPIO-rich LQFP-64 footprint leaves 51 I/O for parallel FPGA-co-bus, NIM-bin clock distribution, or external SRAM hand-shaking. Reference design: ST's AN4073 application note on interleaving ADC channels for higher rates.
Recommandé
Industrial / Building Automation Controllers
The T7 industrial temperature grade of the STM32F405RGT7TR (-40 C to +105 C), combined with the long life-cycle commitment from STMicroelectronics, makes the part a fixture for industrial PLCs, building automation gateways, and HVAC controllers. Two CAN 2.0B interfaces, dual USB OTG, and Ethernet MAC allow simultaneous field-bus, service, and IP-network connectivity in a single chip, replacing discrete transceivers and reducing BOM. The 17 timers with quadrature-encoder support provide closed-loop control of valves, dampers, and pumps without dedicated motion-MCU overhead. Hardware FPU accelerates floating-point control loops; the MPU (Memory Protection Unit) guards against firmware corruption in safety-critical code regions per IEC 61508 SIL-2 patterns. The large 1 Mbyte Flash supports full-featured freeRTOS plus a Modbus or BACnet stack, with the FSMC bus allowing external NOR/SRAM expansion for logging historical trend data. Reference design: ST's STM32-Combi sensor and IO-Link reference firmware for industrial IO hubs.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour STM32F405RGT7TR — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | STM32F407RGT6TR | STM32F405RGT6TR | STM32F405RGT7 | STM32F407RGT7TR | GD32F405RGT7 | GD32F407RGT6 | AT32F405RGT7 |
|---|---|---|---|---|---|---|---|---|
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | GigaDevice | GigaDevice | Artery |
| Package | LQFP-64 (10x10 mm) | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same | LQFP-64 (10x10 mm) - same |
| Core | Cortex-M4F | Cortex-M4F (AES hardware) | Cortex-M4F (no AES) | Cortex-M4F (same die, tray) | Cortex-M4F (AES hardware) | Cortex-M4F (3 MB Flash) | Cortex-M4F (AES hardware) | Cortex-M4F (192 MHz) |
| Max Frequency | 168 MHz | 168 MHz (same) | 168 MHz (same) | 168 MHz (same) | 168 MHz (same) | 168 MHz (same) | 168 MHz (same) | 192 MHz (+14%) |
| Flash | 1 Mbyte | 1 Mbyte (same) | 1 Mbyte (same) | 1 Mbyte (same) | 1 Mbyte (same) | 3 Mbyte (+200%) | 1 Mbyte (same) | 1 Mbyte (same) |
| SRAM | 192 Kbyte + 4 Kbyte CCM | 192 + 4 Kbyte | 192 + 4 Kbyte | 192 + 4 Kbyte | 192 + 4 Kbyte | 256 + 4 Kbyte | 192 + 4 Kbyte | 96 + 0 Kbyte (less) |
| Temperature Grade | Industrial (-40 to +105 C) | Commercial (-40 to +85 C) | Commercial (-40 to +85 C) | Industrial (-40 to +105 C) | Industrial (-40 to +105 C) | Industrial (-40 to +105 C) | Commercial (-40 to +85 C) | Industrial (-40 to +105 C) |
| Hardware AES | No | Yes (AES 128/192/256) | No | No | Yes (AES 128/192/256) | No | Yes | No |
Principaux différenciateurs
- Higher Flash density vs STM32F405RGT6TR and same-package STM32F1 MCU alternatives (vs STM32F405RGT6TR vs STM32F103RGT7)
- Industrial temperature grade T7 vs commercial T6 (vs STM32F405RGT6TR)
- 3 Mbyte Flash in pin-compatible GigaDevice upgrade path (vs GD32F405RGT7)
- Hardware AES engine available on F407 family upgrade (vs STM32F407RGT7TR)
- Higher clock speed on Artery AT32 counter-sourcing option (vs AT32F405RGT7)
Notes de conception
Place a 100 nF X7R ceramic decoupling capacitor within 5 mm of every VDD pin (pins 21, 32, 48, 64), and a single 4.7 uF X5R bulk capacitor near the VDD cluster. VDDA (pin 15) requires its own dedicated 100 nF plus a 1 uF ceramic filter; add a ferrite bead between VDDA and VDD to suppress ADC reference noise during high-current switching events. Avoid routing high-current motor traces under VDDA filtering components - use a GND-fill island or stitched stitching vias below the LQFP thermal pad to keep analog return currents from digital switching noise.
BOOT0 (pin 60) must be tied to GND through 10 kohm for normal Flash boot, or to VDD through 10 kohm to enter the system bootloader for blank-flash programming. Leaving BOOT0 floating is a frequent cause of intermittent boot failures in production. NRST (pin 12) requires an external 10 kohm pull-up to VDD plus a 100 nF capacitor to GND; do not omit the RC network even if external reset is unused - the internal POR is not always sufficient for noisy industrial rails.
Estimated: at maximum 168 MHz with all peripherals active, the LQFP-64 package dissipates approximately 280 mW (per ST family characterization data for STM32F405). The 10x10 mm package has a theta_JA of approximately 45 C/W on a 4-layer JEDEC test PCB, so junction temperature rise is roughly 12.6 C above ambient - well below the 105 C T7 industrial ceiling. For applications running the part at full speed with continuous USB HS streaming, leave at least 0.5 square inches of 2-oz copper connected to the exposed thermal pad footprint pattern; the LQFP-64 lead pitch leads still need this extra copper for thermal spreading.
Keep crystal traces (OSC_IN pin 10, OSC_OUT pin 11) within 5 mm and via-free; place the load capacitors right at the MCU side of these traces. Shield the HSE crystal by routing a GND ring around it. For SD card interfaces using SDIO, route the 4-bit bus with matched trace lengths (delta less than 1 cm) and series-termination resistors near the SD card connector to mitigate reflections at 50 MHz SD card clocks. VREF+ and VREF- should be tied to VDDA and VSSA respectively, with the VDDA/VREF+ pins bridged by a 10 ohm ferrite rather than direct short, to reject upstream regulator noise.
Informations de conformité
RoHS and REACH compliant per ST product page declarations; supplied in lead-free (Pb-free) LQFP-64 packaging. Not AEC-Q100 qualified; for automotive applications choose STM32F405RGT7TR-related automotive SKUs or move to STM32 family autosar-class parts.
