EP20K30EFC144-2X vs EP20K60EFC144-1 तुलना
विस्तृत दोनों ओर की तुलना EP20K30EFC144-2X द्वारा Altera और EP20K60EFC144-1 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K30EFC144-2X | EP20K60EFC144-1 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | Altera APEX 20K | APEX 20KE |
| Device Type | Loadable programmable logic device (FPGA/CPLD hybrid) | — |
| Typical Gates | 30,000 gates | 60,000 |
| Number of Logic Elements / Cells | 1,200 cells (third-party parametric listing) | — |
| Number of Macrocells | 192 | — |
| Number of User I/O | 93 | — |
| Number of Terminals | 144 | — |
| Terminal Form | Ball | — |
| Package Code | LBGA / 144-FBGA | — |
| Package Shape | Square | — |
| Core Supply Voltage | 1.8 V | 1.8 V |
| Process Technology | 0.22 um | — |
| Speed Grade | -2X | -1 |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| ऑपरेटिंग तापमान रेंज | [DATA_NEEDED: exact operating temperature range] | — |
| Embedded RAM Bits | [DATA_NEEDED: embedded memory size] | — |
| Supported I/O Standards | [DATA_NEEDED: supported I/O standards] | — |
| Configuration Schemes | [DATA_NEEDED: supported configuration schemes] | — |
| RoHS स्थिति | unknown | [DATA_NEEDED: rohs_status] |
| Series | — | APEX 20K |
| Logic Family | — | CMOS |
| Maximum System Gates | — | 256,000 |
| Macrocells | — | 256 |
| Maximum User I/Os | — | 93 (per datasheet; 196 max in 144-FBGA family datasheet) |
| Embedded Memory | — | 32,768 bits (2560 RAM blocks) |
| Maximum Internal Frequency | — | 160 MHz |
| Propagation Delay | — | 1.72 ns |
| ऑपरेटिंग तापमान | — | 0 C to 85 C (Commercial) |
| पैकेज | — | 144-FBGA (Fine-pitch BGA) |
| Package Pin Count | — | 144 balls |
| Programming Interface | — | JTAG / ByteBlaster / Altera Programming Unit |