EP20K400CF672C-8 vs EP20K400CF672C8N तुलना
विस्तृत दोनों ओर की तुलना EP20K400CF672C-8 द्वारा Altera और EP20K400CF672C8N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400CF672C-8 | EP20K400CF672C8N |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Logic Elements | 16,640 | — |
| Typical Gates | 400,000 | — |
| Macros | 1,664 | — |
| Maximum User I/O | 488 | 488 |
| Number of I/O Banks | [DATA_NEEDED: number of I/O banks] | — |
| Package Type | PBGA-672 (FineLine BGA, 27 x 27 mm, 1.0 mm pitch) | — |
| Core Voltage (VCCINT) | 1.8 V nominal (1.71 V to 1.89 V) | — |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO options] | — |
| Pin-to-Pin Delay (tPD) | 1.78 ns (speed grade -8) | — |
| Speed Grade | -8 | — |
| Temperature Grade (C) | Commercial, 0 °C to 85 °C | — |
| Process Technology | 0.15 µm all-layer copper CMOS | 0.15 µm all-layer copper CMOS |
| Embedded Memory Type | ESB (RAM / ROM / CAM) | — |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount (BGA) |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance] | — |
| MSL स्तर | [DATA_NEEDED: MSL level] | — |
| Device Logic Elements | — | 16,640 (Macros / Cells) |
| Maximum System Gates | — | 400,000 |
| Embedded Memory | — | 212,992 bits |
| पैकेज | — | 672-ball FineLine BGA (FC-FBGA672) |
| Package Body Size | — | 27 × 27 mm |
| Ball Pitch | — | 1.0 mm |
| Supply Voltage (Core) | — | 1.8 V |
| Logic Family | — | CMOS |
| Propagation Delay | — | 2.5 ns (C speed grade) |
| Maximum Internal Frequency | — | 301.21 MHz |
| ऑपरेटिंग तापमान | — | 0 °C to +85 °C (commercial) |
| Lead-Free / RoHS | — | Yes (N suffix) |