EP20K400GC655-2X vs EP20K400GC655-3X तुलना
विस्तृत दोनों ओर की तुलना EP20K400GC655-2X द्वारा Altera और EP20K400GC655-3X द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400GC655-2X | EP20K400GC655-3X |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) |
| Series | APEX-20KC® | APEX-20KC |
| Logic Elements / Cells | 16640 | 16,640 |
| System Gates | 400000 | 400,000 |
| Total RAM Bits | 212992 | 212,992 bits |
| Number of I/O | 496 | — |
| Number of Dedicated Inputs | 6 | — |
| Number of LABs/CLBs | [DATA_NEEDED: number of Logic Array Blocks] | — |
| Number of EABs | [DATA_NEEDED: number of Embedded Array Blocks] | — |
| Maximum Operating Frequency | 200 MHz | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage (MultiVolt) | 2.5 V / 3.3 V / 5 V | — |
| Package Type | 655-BCPGA (SPGA655) | — |
| Package Body Material | CERAMIC, metal-sealed cofired grid array | — |
| Package Dimensions | 47 x 47 mm | — |
| Peak Reflow Temperature | 220 °C | — |
| माउंटिंग प्रकार | Through-hole (CPGA) | Through-Hole (CPGA, ceramic) |
| Programmability | In-system, JTAG (IEEE 1149.1) | — |
| ऑपरेटिंग तापमान | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| RoHS स्थिति | unknown | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] |
| Manufacturer | — | Altera (now Intel FPGA) |
| Maximum Internal Frequency | — | 167 MHz (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V (LVDS support per APEX 20KE datasheet) |
| पैकेज / केस | — | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) |
| Speed Grade | — | -3 (fastest) |
| Suffix Code | — | -X (extended / ceramic CPGA variant) |
| I/O Count | — | [DATA_NEEDED: max user I/O] |
| JTAG / Boundary Scan | — | IEEE 1149.1 (per APEX 20K family) |