EP20K400GC655-3V vs EP20K400GC655-2X तुलना
विस्तृत दोनों ओर की तुलना EP20K400GC655-3V द्वारा Intel और EP20K400GC655-2X द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP20K400GC655-3V | EP20K400GC655-2X |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Series | APEX-20KC | APEX-20KC® |
| Family | APEX 20KC (Apex 20KE Device Family, 1.8 V, LVDS) | APEX 20K |
| Manufacturer | Altera (now Intel) | — |
| Core Supply Voltage | 1.71 V to 1.89 V (1.8 V nominal) | 2.5 V |
| Logic Elements | 16640 | — |
| Total RAM Bits | 212992 | 212992 |
| Typical Gate Count | 400000 | — |
| Number of User I/O | 496 | — |
| अधिकतम क्लॉक फ़्रीक्वेंसी | 714.2 MHz | — |
| Propagation Delay | 3.6 ns | — |
| Speed Grade | -3V (commercial temperature, Vcc 1.8 V) | — |
| पैकेज | 655-BCPGA (62.48 mm x 62.48 mm) | — |
| Package Equivalence Code | SPGA655, 47x47 | — |
| माउंटिंग प्रकार | Through Hole (CPGA) | Through-hole (CPGA) |
| Peak Reflow Temperature | 220 C | 220 °C |
| Process Technology | CMOS | 0.22 µm CMOS |
| Configuration | SRAM-based (requires EPC configuration device) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance flag - BCPGA package often non-RoHS] | unknown |
| ऑपरेटिंग तापमान | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: temperature grade] |
| Logic Elements / Cells | — | 16640 |
| System Gates | — | 400000 |
| Number of I/O | — | 496 |
| Number of Dedicated Inputs | — | 6 |
| Number of LABs/CLBs | — | [DATA_NEEDED: number of Logic Array Blocks] |
| Number of EABs | — | [DATA_NEEDED: number of Embedded Array Blocks] |
| Maximum Operating Frequency | — | 200 MHz |
| I/O Supply Voltage (MultiVolt) | — | 2.5 V / 3.3 V / 5 V |
| Package Type | — | 655-BCPGA (SPGA655) |
| Package Body Material | — | CERAMIC, metal-sealed cofired grid array |
| Package Dimensions | — | 47 x 47 mm |
| Programmability | — | In-system, JTAG (IEEE 1149.1) |