EP2A40B724C7 vs EP2A40B724C8ES तुलना
विस्तृत दोनों ओर की तुलना EP2A40B724C7 द्वारा Intel और EP2A40B724C8ES द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP2A40B724C7 | EP2A40B724C8ES |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | APEX II | Field Programmable Gate Array (FPGA) |
| Logic Elements / Cells | 38,400 | 38,400 |
| Total System Gates | 1,500,000 | — |
| Embedded RAM Bits | 655,360 | — |
| Maximum User I/O | 540 | — |
| Core Supply Voltage | 1.425 V to 1.575 V (typ. 1.5 V) | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers, all-layer copper | — |
| Maximum Internal Frequency | 562 MHz | — |
| PLLs | 4 | — |
| पैकेज | 724-ball FCBGA (FineLine BGA), 35 mm x 35 mm | 724-BBGA / FCBGA |
| ऑपरेटिंग तापमान | 0 °C to +85 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| I/O Standards Supported | LVTTL, LVCMOS, 1.5 V/1.8 V/2.5 V/3.3 V, SSTL, HSTL, PCI, LVDS, LVPECL, PCML, HyperTransport, True-LVDS (1 Gbps) | — |
| Configuration Method | JTAG (IEEE 1149.1), Passive Serial, Passive Parallel, Active Serial via EPC configuration devices | — |
| MultiVolt I/O Support | 1.5 V, 1.8 V, 2.5 V, 3.3 V | — |
| DDR Memory Support | Yes (via ESB / I/O circuitry) | — |
| RoHS स्थिति | Non-compliant (lead-bearing FCBGA) | [DATA_NEEDED: RoHS status] |
| MSL स्तर | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL moisture sensitivity level] |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount |
| Series | — | APEX II (EP2A) |
| Number of Gates (typical) | — | 655,360 |
| Number of I/O | — | 540 |
| Speed Grade | — | -8 (C8) |
| सप्लाई वोल्टेज | — | [DATA_NEEDED: VCCINT / VCCIO core and I/O voltages] |
| Process Node | — | [DATA_NEEDED: CMOS process technology] |
| Embedded Memory | — | Embedded System Blocks (ESB) |
| Programmable Logic Type | — | SRAM-based, in-system reconfigurable |
| Lead-Free Status | — | [DATA_NEEDED: lead-free status] |
| Architecture | — | MultiCore interconnect with LABs and ESBs |