EP2S130F1020C5N vs EP2S130F780C5 तुलना
विस्तृत दोनों ओर की तुलना EP2S130F1020C5N द्वारा Intel और EP2S130F780C5 द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP2S130F1020C5N | EP2S130F780C5 |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | Obsolete |
| Family | Stratix II | Stratix II |
| Logic Elements | 132,540 | 132,540 |
| Adaptive Logic Modules (ALMs) | 6627 LABs (per Jotrin listing) | — |
| Total Memory Bits | 6,747,840 bits | — |
| User I/Os | 734 | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Core Supply Voltage (VCCINT) | 1.15 V to 1.25 V | — |
| Maximum Internal Frequency | 609.76 MHz | — |
| पैकेज | 1020-ball FC-FBGA (33x33 mm) | 780-FBGA (FC-FBGA), 29 mm x 29 mm |
| माउंटिंग प्रकार | Surface Mount | — |
| ऑपरेटिंग तापमान | Commercial (0C to +85C, C5 grade) | 0 C to +85 C (TJ) |
| Temperature Grade | C5 (other - per Partstack) | — |
| RoHS स्थिति | [DATA_NEEDED: rohs status] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| PLLs | 4 (typical Stratix II feature) | — |
| Global Clock Networks | 16 (typical Stratix II feature) | — |
| Configuration Method | Serial/Parallel via Quartus II (typical Stratix II) | — |
| Country of Origin | Republic of Korea (per GlobalSpec) | — |
| ECCN | 3A001.a.7.a (per GlobalSpec) | — |
| Estimated EOL Date | 2023 (per GlobalSpec) | — |
| Logic Array Blocks (LABs) | — | 6627 |
| User I/O Count | — | 534 |
| Embedded Memory (bits) | — | 6,737,280 |
| Embedded 18x18 Multipliers | — | 252 |
| Core Voltage (VCCINT) | — | 1.15 V to 1.25 V (typ. 1.2 V) |
| Internal Clock Frequency (max) | — | 609.76 MHz |
| Speed Grade | — | C5 |
| Lead-Free / RoHS | — | Lead Free / RoHS Compliant |
| Configuration Interface | — | JTAG (IEEE 1149.1) + Passive Serial / Fast Passive Parallel |
| DSP Performance | — | Up to ~1.4 GMACs (per family datasheet) |