EP610DC-15 vs EP610DC-35 तुलना
विस्तृत दोनों ओर की तुलना EP610DC-15 द्वारा Altera और EP610DC-35 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP610DC-15 | EP610DC-35 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | NRND |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 35 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| ऑपरेटिंग तापमान | 0C to 70C (commercial) | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| पैकेज | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| माउंटिंग प्रकार | Through-Hole | Through-Hole (DIP) |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Device Type | — | CPLD - Classic EPLD |
| Family | — | Altera Classic EP610 |
| Usable Gates | — | 300 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |