EP910DI-30 vs EP910DI-35 तुलना
विस्तृत दोनों ओर की तुलना EP910DI-30 द्वारा Rochester Electronics और EP910DI-35 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrndविशेषता तुलना
| पैरामीटर | EP910DI-30 | EP910DI-35 |
|---|---|---|
| ब्रांड | Rochester Electronics | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | सक्रिय |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD (Altera EP910 series) | Altera Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM |
| पैकेज | CDIP-40 (ceramic DIP, 40-pin with UV window) | CDIP-40 (Ceramic DIP with UV window) |
| माउंटिंग प्रकार | Through-Hole (DIP) | Through-Hole |
| Dedicated Inputs | 10 | 10 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| पिन काउंट | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| ऑपरेटिंग तापमान | -40C to +85C (industrial) | -40C to +85C (industrial) |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Toggle Frequency (fCNT) | — | 28.6 MHz |
| Supply Current (ICC) | — | 40 mA typical |
| Bidirectional I/O Pins | — | 20 |
| Total Pins | — | 40 |
| Programming Method | — | EPROM programmer + JEDEC fuse map |
| Erasure Method | — | UV light through quartz window |
| Logic Family | — | PAL-type AND/OR array with D flip-flops |
| Manufacturer | — | Original Altera; long-term authorized by Rochester Electronics, LLC |