EP910IPC-15 vs EP910IDC-15 तुलना
विस्तृत दोनों ओर की तुलना EP910IPC-15 द्वारा Altera और EP910IDC-15 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EP910IPC-15 | EP910IDC-15 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V |
| ऑपरेटिंग तापमान | 0C to +70C (commercial, IPC suffix) | — |
| पैकेज | PDIP-40 (Plastic DIP, 40-pin) | 40-pin CDIP (Ceramic DIP, through-hole) |
| माउंटिंग प्रकार | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| पिन काउंट | 40 | — |
| RoHS स्थिति | [DATA_NEEDED: rohs status not confirmed in verified data] | non_compliant (ceramic DIP contains lead) |
| Manufacturer | — | Altera (now Intel PSG) |
| Family | — | Classic EPLD |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| Programming Technology | — | EPROM (UV-erasable) |