EPF10K200SFC672-2 vs EPF10K200SFC672-1X तुलना
विस्तृत दोनों ओर की तुलना EPF10K200SFC672-2 द्वारा Altera और EPF10K200SFC672-1X द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPF10K200SFC672-2 | EPF10K200SFC672-1X |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | NRND | Obsolete |
| Series | FLEX 10KE | FLEX-10KS |
| Logic Elements | 9,984 | — |
| System Gates | 200,000 | — |
| Logic Array Blocks (LABs) | 1,248 | 1,248 |
| User I/O Pins | 470 | 470 |
| Embedded Memory (bits) | 98,304 | — |
| Process Technology | 0.22 µm CMOS | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Speed Grade | -2 | — |
| Internal Propagation Delay | 0.4 ns | — |
| Maximum Operating Frequency | 200 MHz | — |
| पैकेज | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch | 672-ball FineLine BGA, 27 × 27 mm, 1.0 mm pitch |
| ऑपरेटिंग तापमान | 0 °C to +70 °C (Commercial) | 0 °C to 70 °C (Commercial) |
| Configuration Method | SRAM-based, passive parallel asynchronous | SRAM (volatile, reconfigurable at every power-up) |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| On-chip PLL | Yes | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | FLEX 10K (legacy) |
| Architecture | — | Reconfigurable CMOS SRAM |
| Typical System Gates | — | 200,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gate count] |
| Logic Elements (LEs) | — | 9,984 |
| Embedded Array Blocks (EABs) | — | 24 |
| Embedded RAM Bits | — | 98,304 |
| Propagation Delay | — | 0.4 ns |
| JTAG Support | — | IEEE Std. 1149.1 (adds up to 31,250 gates) |
| माउंटिंग प्रकार | — | Surface Mount |
| Logic Family | — | CMOS |
| Design Tool | — | Quartus (legacy FLEX 10K support) |