EPF10K50EQI240-2N vs EPF10K50EQC240-1N तुलना
विस्तृत दोनों ओर की तुलना EPF10K50EQI240-2N द्वारा Intel और EPF10K50EQC240-1N द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EPF10K50EQI240-2N - 50K-Gate FLEX 10KE FPGA, 240 PQFP | Intel / Altera
EPF10K50EQI240-2N ObsoleteAltera
EPF10K50EQC240-1N - FLEX 10KE FPGA 50K Gates 2880 Cells 240-PQFP | Altera
EPF10K50EQC240-1N Obsoleteविशेषता तुलना
| पैरामीटर | EPF10K50EQI240-2N | EPF10K50EQC240-1N |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | FLEX 10KE | FLEX 10KE |
| Logic Elements / Cells | 2880 | 2880 |
| Total RAM Bits | 40960 | 40960 |
| Number of LABs / CLBs | 360 | — |
| Maximum System Gates | 199000 | — |
| User I/O Pins | 189 | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Core Supply Voltage (VCCINT) | 2.5 V | — |
| I/O Supply Voltage (VCCIO) | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Internal Frequency (max) | 66.67 MHz | — |
| Propagation Delay (per LE) | 0.6 ns | — |
| Process Technology | 0.22 µm CMOS, SRAM-based | 0.22 µm CMOS |
| Package Type | 240-pin PQFP / BQFP (FQFP, gull-wing) | — |
| माउंटिंग प्रकार | Surface Mount (SMD/SMT) | Surface Mount (PQFP) |
| ऑपरेटिंग तापमान | -40 °C to +85 °C (Industrial) | 0 °C to +85 °C (Commercial) |
| Configuration Method | SRAM (volatile) — requires external EPC PROM | — |
| Embedded Memory | Embedded Array Blocks (EABs), configurable as RAM/ROM/FIFO | — |
| Logic Family | CMOS | — |
| RoHS स्थिति | unknown | [DATA_NEEDED: RoHS status] |
| Number of Logic Gates | — | 50K |
| Number of LABs/CLBs | — | 360 LABs |
| Number of I/O | — | 189 |
| Supply Voltage (Core) | — | 2.5 V |
| Supply Voltage (I/O MultiVolt) | — | 2.5 V / 3.3 V / 5 V |
| Maximum Internal Frequency | — | 250 MHz |
| Propagation Delay | — | 0.5 ns |
| पैकेज | — | 240-pin PQFP / BFQFP |
| Configuration Mode | — | Passive Serial (PS), JTAG |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Lead Free | — | [DATA_NEEDED: lead-free status] |