EPF8820ARC208-3 vs EPF8636ARC208-4 तुलना
विस्तृत दोनों ओर की तुलना EPF8820ARC208-3 द्वारा Intel और EPF8636ARC208-4 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 Obsolete
विशेषता तुलना
| पैरामीटर | EPF8820ARC208-3 | EPF8636ARC208-4 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Series | FLEX 8000 | — |
| Family | FLEX 8000 (EPF8820) | — |
| Usable Gates | 8,000 | 6,000 |
| Logic Cells / Elements | 672 | — |
| Registers | 152 | — |
| Maximum Operating Frequency | 125 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Process Technology | 0.42 µm CMOS | 5 V CMOS, 0.42 um |
| Configuration Memory | SRAM (volatile) | — |
| पैकेज / केस | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) | — |
| Supplier Device Package | 208-RQFP (28x28) | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| Packaging | Tray | — |
| ऑपरेटिंग तापमान रेंज | [DATA_NEEDED: operating temperature range] | — |
| In-Circuit Reconfigurability (ICR) | Yes (via external configuration devices) | — |
| Boundary-Scan Test | JTAG (IEEE 1149.1) | — |
| I/O Tolerance | 3.3 V / 5 V | — |
| Clock Networks | 4 dedicated low-skew global clocks | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | Non-compliant (legacy 5 V family) |
| Lead-Free / Finish | [DATA_NEEDED: lead-free finish] | — |
| Product Family | — | FLEX 8000 |
| Device Series | — | EPF8636A |
| Logic Elements | — | 136 |
| Flip-Flops (Registers) | — | 504 |
| Maximum User I/O | — | 218 |
| Embedded RAM Blocks | — | 8 x 256 x 8 bits |
| Logic Block Type | — | 4-input LUT with fast-carry chain |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V |
| Speed Grade | — | -4 |
| ऑपरेटिंग तापमान | — | -40 C to +105 C |
| पैकेज | — | 208-RQFP (28x28 mm) with exposed pad |
| Configuration Method | — | Serial configuration EEPROM (in-system) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |