EPM3512AQC20810 vs EPM3512AQC208-10S तुलना
विस्तृत दोनों ओर की तुलना EPM3512AQC20810 द्वारा Altera और EPM3512AQC208-10S द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM3512AQC20810 | EPM3512AQC208-10S |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Logic Type | CPLD (EEPROM-based, non-volatile) | — |
| Macro Cells | 512 | — |
| User I/Os | 172 | 208 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Usable Gates (equivalent) | 10000 | — |
| पैकेज | 208-pin PQFP (PQ208) | 208-pin FineLine BGA-256 |
| Speed Grade | -10 (tPD = 10 ns) | -10 (tPD1 = 7.5 ns) |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 132 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG, 3.3 V ISP) | — |
| PCI Compliance | PCI Local Bus Specification Revision 2.2 compliant | Yes (PCI Local Bus Specification Rev 2.2) |
| Operating Temperature (commercial) | 0 °C to +70 °C | — |
| Process Technology | 0.30 µm CMOS EEPROM | EEPROM-based CMOS |
| Configuration Memory | On-chip EEPROM, non-volatile, 100+ cycles, 10+ year retention | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs_status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Usable Gates | — | 1750 |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| ऑपरेटिंग तापमान | — | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |