EPM5192GI84 vs EPM5192JC84-1 तुलना
विस्तृत दोनों ओर की तुलना EPM5192GI84 द्वारा Altera और EPM5192JC84-1 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5192GI84 | EPM5192JC84-1 |
|---|---|---|
| ब्रांड | Altera | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable / OTP Complex PLD (CPLD) | UV-Erasable/OTP Complex Programmable Logic Device (CPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks | [DATA_NEEDED: number of LABs] | — |
| पैकेज | 84-pin PGA (WPGA, square, through-hole, pin/peg terminals) | 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) |
| Package Code | WPGA | — |
| Operating Voltage (VCC) | 5 V (typical) | — |
| I/O Logic Compatibility | TTL | — |
| Temperature Grade | Industrial | — |
| Programmable Flip-Flop Modes | D, T, JK, SR | — |
| Programmability | UV-erasable (windowed) / OTP | UV-erasable (window) / OTP in production |
| Programming File Format | JEDEC map via MAX+PLUS II / A+PLUS | — |
| Propagation Delay | [DATA_NEEDED: tPD in ns] | — |
| Max User I/O Pins | [DATA_NEEDED: usable I/O count for this package] | — |
| ऑपरेटिंग तापमान रेंज | -40 C to +85 C (industrial) | — |
| माउंटिंग प्रकार | Through-Hole (PGA socket or PCB pin/peg) | Surface Mount |
| RoHS स्थिति | [DATA_NEEDED: most legacy PGA parts are non-RoHS] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: legacy part, likely contains lead] | — |
| Number of Terminals | 84 | — |
| Terminal Form | PIN/PEG | J-BEND |
| Package Shape | SQUARE | SQUARE |
| Propagation Delay (tpd) | — | 40 ns (worst case) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V ±5 %) |
| Process Technology | — | CMOS EPROM |
| Operating Temperature Grade | — | Commercial |
| JESD-30 Package Code | — | S-CQCC-J84 |
| Configuration Memory | — | EPROM (non-volatile, instant-on) |