EPM5192JC1 vs EPM5192JC-1N तुलना
विस्तृत दोनों ओर की तुलना EPM5192JC1 द्वारा Intel और EPM5192JC-1N द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5192JC1 | EPM5192JC-1N |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 5000 (MAX 5xxx CPLD) | MAX 5000 |
| Manufacturer | Intel (formerly Altera Corporation) | — |
| Macro Cells | 192 | — |
| Usable Gates | 3750 | 3750 |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 4.75 V to 5.25 V |
| Process Technology | 0.5 µm CMOS, UV-erasable EPROM | — |
| Propagation Delay (typ) | [DATA_NEEDED: propagation delay in ns] | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| पैकेज | [DATA_NEEDED: exact package from datasheet] | 84-pin Ceramic Quad Flat Pack (CQFP) |
| माउंटिंग प्रकार | [DATA_NEEDED: surface mount or through-hole] | — |
| ऑपरेटिंग तापमान | [DATA_NEEDED: operating temp range] | [DATA_NEEDED: industrial/commercial temperature range] |
| Programming Interface | JTAG-compatible (Altera MAX 5xxx) | JTAG / Altera ByteBlaster |
| Logic Blocks (LABs) | 24 (8 macrocells per LAB) | — |
| RoHS स्थिति | unknown | — |
| AEC-Q100 | not_applicable | — |
| Lifecycle | Obsolete - last-time-buy stock only at franchised distributors | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs (GCLK) | — | 1 |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| Technology | — | CMOS EPROM (UV-erasable) |
| JEDEC Package Code | — | S-CQCC-J84 |