EPM9560RC304-2N vs EPM9560RC304-5 तुलना
विस्तृत दोनों ओर की तुलना EPM9560RC304-2N द्वारा Intel और EPM9560RC304-5 द्वारा Altera. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM9560RC304-2N | EPM9560RC304-5 |
|---|---|---|
| ब्रांड | Intel | Altera |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | Complex Programmable Logic Device (CPLD) / EPLD |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | [DATA_NEEDED: number of LABs] |
| Maximum User I/O | [DATA_NEEDED: user I/O count] | — |
| पैकेज | RQFP/RBGA-class 304-pin plastic carrier (RC304) | 304-pin RQFP (PowerQuad II) |
| Speed Grade | -2 (mid-band) | -5 (fastest grade in family) |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD value in ns] | [DATA_NEEDED: propagation delay] |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage Tolerance | 5.0 V (3.3 V with level shifting) | — |
| Programming Technology | EPROM/EEPROM, non-volatile | — |
| In-System Programming | IEEE 1149.1 JTAG | — |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | — |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | ROHS3 Compliant |
| माउंटिंग प्रकार | Surface Mount | Surface Mount |
| MSL स्तर | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | MAX 9000 (EPM9560) |
| Maximum Operating Frequency | — | 117.6 MHz (family -15 grade reference) |
| सप्लाई वोल्टेज | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes (JTAG ISP) |
| नमी संवेदनशीलता स्तर (MSL) | — | 3 (168 Hours) |
| Manufacturer Standard Lead Time | — | 1-7 Days (distributor listing) |
| ऑपरेटिंग तापमान रेंज | — | [DATA_NEEDED: operating temperature range] |
| Number of I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |