SN74LS90N - 4-Bit Decade Counter | Texas Instruments
MPN: SN74LS90N ✓ सक्रियSN74LS90N अवलोकन
A decade counter is a synchronous-state counter built from flip-flops and logic gates. In the broader electronics hierarchy, a decade counter belongs to counter logic, digital logic ICs, logic ICs, and ultimately semiconductor devices. It is commonly used to divide one input frequency into lower, predictable frequencies or to produce a modulo-10 counting sequence for timing and control functions.
The SN74LS90N provides a 4-bit counter element, negative-edge triggering, and upward counting. Its TTL-compatible interface allows it to operate with other 74LS-family digital logic in established industrial control, instrumentation, and legacy computer systems. Because its counting architecture includes independently controlled sections, designers can also use it in divide-by-five, divide-by-six, divide-by-eight, and related applications depending on the selected output connections.
Technically, the monolithic counter combines four master-slave flip-flops with additional gating logic. The master-slave arrangement helps prevent race-through conditions when the clock changes state, while negative-edge triggering defines exactly when the stored count advances. Designers should still account for propagation delay, setup and hold requirements, and output transition behavior when operating near the device’s maximum clock frequency.
Typical uses include digital timing references, industrial sequence counters, frequency-divider circuits, test equipment, and embedded legacy control systems. The SN74LS90N is especially appropriate when an existing board requires a standard 14-pin TTL counter rather than a programmable modern counter. Availability and lifecycle decisions should be based on current distributor inventory because legacy through-hole logic sourcing can vary.
The primary design consideration is timing margin. Confirm the selected output’s transition timing against the load and the next device’s setup requirement, and route the clock to minimize ringing. Decoupling close to the supply pins and careful grounding remain necessary because every counter edge can propagate supply and ground disturbance into adjacent logic.
This page combines verified manufacturer and distributor information, package details, pricing context, sourcing guidance, and verified drop-in alternatives. It also distinguishes documented facts from parameters that still require confirmation from the manufacturer datasheet, helping engineers avoid unsupported assumptions during legacy-logic maintenance and redesign.
के लिए ड्रॉप-इन विकल्प SN74LS90N — समान पैकेज, पिन-टू-पिन संगत। PCB रीवर्क आवश्यक करने वाले भिन्न-पैकेज पार्ट्स शामिल नहीं हैं।
SN74LS90AP
✅ ड्रॉप-इन ⚠️ विनिर्देश असत्यापित📋 संदर्भ विकल्प (कैटलॉग में नहीं)
SN74LS90BP
✅ ड्रॉप-इन ⚠️ विनिर्देश असत्यापित📋 संदर्भ विकल्प (कैटलॉग में नहीं)
SN74HCT90N
✅ ड्रॉप-इन📋 संदर्भ विकल्प (कैटलॉग में नहीं)
SN74LS90N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →SN74LS90N Maximum Ratings और Electrical Characteristics
| Counter Type | Decade counter |
| Number of Counter Elements | 1 element |
| Counter Width | 4 bit |
| Counting Direction | Up |
| Counting Mode | Asynchronous |
| Triggering Edge | Negative edge |
| Logic Family | LS-series TTL |
| Internal Count Sequence | Divide-by-five for the 74LS90 |
| Internal Architecture | Four master-slave flip-flops with additional gating |
| Package Type | 14-pin PDIP |
| माउंटिंग प्रकार | Through-hole |
SN74LS90N 14-pin pdip पिन कॉन्फ़िगरेशन गाइड
SN74LS90N (14-pin pdip पैकेज) के लिए पिन कॉन्फ़िगरेशन। इस डिजिटल IC में GPIO, संचार इंटरफ़ेस (UART, SPI, I2C) और पावर पिन शामिल हैं। वैकल्पिक पिन फ़ंक्शन और कॉन्फ़िगरेशन विकल्पों के लिए निर्माता डेटाशीट देखें। एम्बेडेड सिस्टम डिज़ाइन और PCB लेआउट के लिए आवश्यक।
इसके लिए कोई विस्तृत pinout data उपलब्ध नहीं: SN74LS90N.
देखें डेटाशीट पूर्ण पिन कॉन्फ़िगरेशन के लिए।
सामान्य अनुप्रयोग
SN74LS90N के लिए उपयुक्त है 6 अनुप्रयोगs: Digital Frequency Divider, Industrial Sequence Control, Test and Measurement Timing, Legacy Computer Control, Pulse and Event Counting, Teaching and Logic Prototyping.
Digital Frequency Divider
The SN74LS90N fits fixed frequency-divider and clock-generation circuits because it is a 4-bit asynchronous decade counter with negative-edge triggering. The manufacturer describes four master-slave flip-flops with additional gating and a divide-by-five count cycle for the 74LS90 family, allowing selectable outputs to establish different division relationships. In a legacy timing circuit, the counter can reduce a repetitive input clock while preserving the established 14-pin PDIP footprint. The primary design check is timing margin: propagation delay from the clock edge to the selected output must remain below the period available before the next active edge and must satisfy the receiving device’s setup requirement.
अनुशंसित
Industrial Sequence Control
The SN74LS90N is suitable for legacy industrial sequence control where a simple modulo-10 count is preferable to a programmable counter. Its 4-bit, upward-counting, asynchronous architecture provides predictable state advancement on each negative clock edge, while the TTL interface supports integration with established 74LS-family control logic. A maintenance engineer can use it for repeatable machine-event indexing, actuator sequencing, or discrete timing stages without redesigning the board footprint. Because timing behavior depends on propagation and transition delays, the design should verify the selected counter outputs against actuator relay-driver timing and prevent switch bounce or contact noise from propagating into the clock input.
अनुशंसित
Test and Measurement Timing
The SN74LS90N can serve as a fixed timing and counting element in test equipment where a stable, hardware-driven decade sequence is required. Its four master-slave flip-flops and additional gating implement the documented divide-by-five count cycle, making it useful when a test system needs repeatable intervals or numbered measurement stages. The negative-edge trigger defines when the count advances and allows the circuit to be synchronized with other legacy timing logic. When using the device in instrumentation, keep the clock distribution short, provide local supply bypassing, and compare the selected output’s delay with the measurement system’s acquisition and settling requirements.
अनुशंसित
Legacy Computer Control
The SN74LS90N is appropriate for maintaining a legacy computer or control system that requires a through-hole decade counter rather than a modern programmable or surface-mount device. Its 14-pin PDIP package supports repair and board-level substitution workflows, and the asynchronous negative-edge count behavior fits established TTL control schemes. The part can index recurring operations, divide a system clock, or generate a modulo-10 state sequence for peripheral control. Retrofitting requires more than package compatibility: confirm supply voltage, input thresholds, output levels, timing margins, and environmental requirements against the original system documentation before approving the replacement.
अनुशंसित
Pulse and Event Counting
The SN74LS90N can be used for pulse counting in low-speed event-counting, batch, or indexing systems because it provides a 4-bit up counter with negative-edge triggering. Multiple output taps provide visibility into internal count states, allowing external control logic to decode selected stages or use the counter as a repeatable event divider. This is useful when the input events are already conditioned and the required count range is fixed. Practical implementation should include input conditioning for noisy mechanical contacts, account for clock pulse width and setup time, and ensure that the selected output remains stable for the acquisition or decoding circuit.
अनुशंसित
Teaching and Logic Prototyping
The SN74LS90N is useful in electronics education and logic-prototyping benches because its through-hole package is easy to install and its internal counter states can be observed at accessible outputs. Students or engineers can demonstrate decade counting, negative-edge triggering, gated divisions, and interactions between 74LS-family logic on a common 5 V TTL-style board. The Texas Instruments datasheet describes the four master-slave flip-flops and extra gating that create the counter’s internal behavior, making the device a practical platform for tracing causality between clock transitions and output states. Projects should still follow safe assembly practices and use the manufacturer pinout and electrical limits rather than inferring connections from a generic 74LS90 drawing.
अनुशंसित
अनुशंसित उत्पादों का सारांश
के लिए इंजीनियरिंग संदर्भ डेटा SN74LS90N — तुलना, डिज़ाइन मार्गदर्शन और अनुपालन जानकारी।
चयन गाइड
विकल्पों के साथ तुलना
| पैरामीटर | यह उत्पाद | SN74LS90AP | SN74LS90BP | SN74HCT90N | SN74LS90N |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | onsemi |
| Package | 14-pin PDIP | PDIP-14 | PDIP-14 | PDIP-14 | PDIP-14 |
| Counter Type | Decade counter | Decade counter | Decade counter | Decade counter | Decade counter |
| Logic Family | LS-series TTL | LS-series TTL | LS-series TTL | HCT TTL-compatible CMOS | LS-series TTL |
मुख्य विशेषताएँ
- Original Texas Instruments 74LS90 sourcing (बनामonsemi SN74LS90N)
- Mixed-logic input compatibility (बनामSN74HCT90N)
- Standard 14-pin through-hole integration (बनामSN74LS90AP)
- Negative-edge-triggered fixed counting (बनामSN74LS90BP)
डिज़ाइन नोट्स
Do not infer pin assignments from a generic 74LS90 drawing. The supplied evidence confirms the SN74LS90N uses a 14-pin PDIP, but it does not reproduce the individual pin names. Download the official Texas Instruments PDF and verify clock, clear, enable, supply, ground, and output connections against the actual PCB footprint. Also confirm the negative-edge trigger and the selected output's timing before exchanging the device.
Treat the clock net as a potentially high-speed edge even when the counter operates at a low repetition rate. Keep the clock route short, minimize stub branches, and place any required damping close to the driver. Because the device advances on the negative edge, a ringing or double transition at that edge can cause an unintended count increment. Confirm the received waveform at the IC pin rather than relying only on a source-side measurement.
Provide local supply bypassing at the IC and route the return current through a low-impedance ground path. Counter outputs transition simultaneously with internal clock activity, so inadequate decoupling can couple supply disturbance into adjacent 74LS logic. The supplied snippets do not include the device's supply range or current consumption, so obtain those limits from the manufacturer datasheet before selecting capacitors or planning power-budget headroom.
A same-function counter is not automatically a drop-in replacement. For the SN74HCT90N and onsemi SN74LS90N, verify pinout, input thresholds, output levels, propagation delay, maximum clock frequency, temperature range, and power limits in the relevant manufacturer datasheet. In mixed TTL/CMOS systems, HCT input compatibility can be advantageous, but it may also alter noise margins and should be reviewed against the complete interface.
अनुपालन जानकारी
The supplied verified results do not provide explicit RoHS, REACH, lead-free, halogen-free, or conflict-minerals declarations. No AEC-Q100 qualification is identified in the supplied evidence.
