5CSEBA4U19C7N vs 5CSEBA5U19C7N Perbandingan
Perbandingan bersamaan detil 5CSEBA4U19C7N dari Intel dan 5CSEBA5U19C7N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
5CSEBA4U19C7N - Cyclone V SE SoC FPGA, 40K LE, Dual ARM Cortex-A9 | Intel
5CSEBA4U19C7N ✓ AktifPerbandingan Spesifikasi
| Parameter Umum | 5CSEBA4U19C7N | 5CSEBA5U19C7N |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Series | Cyclone V SE SoC FPGA | — |
| Family | 5CSEBA4 (U19 device) | Cyclone V SE SoC FPGA |
| Logic Elements | 40 K | 85,000 |
| HPS Cores | Dual ARM Cortex-A9 MPCore with CoreSight | — |
| HPS Max Frequency | 800 MHz | — |
| DSP Blocks | Variable-precision DSP (number not specified in data) | Variable-precision, 18x18 / 27x27 multipliers |
| Embedded Memory | [DATA_NEEDED: total Kbits of embedded RAM] | M10K + MLAB blocks, ~4,450 Kbits total |
| Embedded Multipliers | 56 (18x18) | — |
| PLLs | 4 | — |
| Hard Memory Controllers | 2 | — |
| Hard USB 2.0 OTG | Yes | — |
| Hard PCIe Gen2 | Yes (rootport/endpoint configurable) | — |
| Core Voltage | 1.1 V | — |
| Process Technology | 28 nm low-power | — |
| Suhu Kerja | 0 C to +85 C (commercial) | 0C to +85C (commercial, junction) |
| Paket | 484-pin UBG A (UBGA), 19x19 mm | 484-UBGA (UBGAmobile, 19x19 mm) |
| AES Encryption | Supported | — |
| SEU Error Detection/Correction | Supported | — |
| Configuration Interface | JTAG | — |
| Status RoHS | Compliant | — |
| Hard Processor System | — | Dual ARM Cortex-A9 MPCore with CoreSight |
| HPS Maximum Frequency | — | 800 MHz per core |
| Speed Grade | — | -7 (standard) |
| Process Node | — | 28 nm low-power (TSMC) |
| Supply Voltage (Core) | — | 1.1 V typical |
| HPS Peripherals | — | EMAC, USB 2.0 OTG, NAND, DDR3, SPI, QSPI, I2C, UART |
| Tipe Mounting | — | Surface Mount (BGA) |
| RoHS / Pb-free | — | Yes |
| Configuration Memory | — | External (active serial via HPS or FPGA) |
| Level MSL | — | 3 (per JEDEC J-STD-020, reflow 260C) |
| Block Pins (User I/O) | — | Approximately 66 user I/O pins |