A42MX09-PQG160A vs A42MX09-2PQG160 Perbandingan

Perbandingan bersamaan detil A42MX09-PQG160A dari Microchip Technology dan A42MX09-2PQG160 dari Microchip Technology. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Microchip Technology
A42MX09-PQG160A A42MX09-PQG160A - 14K Gate 5V FPGA 101 I/O | Microchip

A42MX09-PQG160A - 14K Gate 5V FPGA 101 I/O | Microchip

A42MX09-PQG160A ✓ Aktif
Microchip Technology
A42MX09-2PQG160 A42MX09-2PQG160 - 14K Gate 5V FPGA, 160-BQFP | Microchip

A42MX09-2PQG160 - 14K Gate 5V FPGA, 160-BQFP | Microchip

A42MX09-2PQG160 ✓ Aktif

Perbandingan Spesifikasi

Parameter Umum A42MX09-PQG160A A42MX09-2PQG160
Merek Microchip Technology Microchip Technology
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Family 42MX (MX FPGA) MX (Actel/Microsemi antifuse FPGA)
System Gates 14000 gates 14000
Logic Cells 336 —
User I/O 101 101
Tegangan Pemuat 5 V (core/I/O), 3.3 V supported —
Process Technology 0.45 um CMOS antifuse —
Programming Technology Antifuse (one-time programmable) Antifuse (one-time programmable, non-volatile)
Maximum Toggle Frequency 129 MHz / 215 MHz (per FPGAkey listing) —
Paket 160-BQFP / PQFP-160 (28x28 mm) 160-BQFP (PQFP-160, 28x28 mm)
Tipe Mounting Surface Mount Surface Mount
Suhu Kerja [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range]
Speed Grade Standard (see suffix; 'A' package variant) -2
Configuration Non-volatile, instant-on (no boot PROM) —
Lead Free Yes (G suffix, per Kynix: LEAD FREE) —
Status RoHS Compliant (per LCSC listing) Compliant (G = lead-free suffix)
Packaging Tray —
Level MSL [DATA_NEEDED: MSL rating] —
Configurable Logic Blocks (CLBs) — 336
Max Clock Frequency — 146.3 MHz
Supply Voltage Architecture — 5.0 V
Moisture Sensitivity Level — [DATA_NEEDED: MSL level]
Lifecycle / Screening Suffix — Standard commercial/industrial (no M/A suffix)
Typical Use — Single-chip ASIC alternative, legacy 5V PLD integration

Spek dan Sumber

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