EP1810GM883B vs EP1810JC-35 Perbandingan
Perbandingan bersamaan detil EP1810GM883B dari Altera dan EP1810JC-35 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP1810GM883B | EP1810JC-35 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Device Family | EP1810 (Classic EPLD) | Classic EPLD (EP1810) |
| Macrocells | 48 | — |
| User Flip-Flops | Up to 64 | — |
| Total Inputs | 60 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 (bidirectional, tri-state) | — |
| Propagation Delay (tPD) | 50 ns max | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-erasable | — |
| Suhu Kerja | -55 °C to +125 °C (Military, MIL-STD-883B) | — |
| Package Type | Ceramic Pin Grid Array (PGA), 84 pins | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Package Designator | GM (ceramic PGA) | — |
| Processing Level | MIL-STD-883B (Class B) | — |
| Programming Method | UV-erasable / Altera programming hardware | — |
| Tipe Mounting | Through-hole (PGA socket or PCB through-hole) | Surface Mount (J-Lead) |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status] | — |
| Logic Family | TTL-compatible I/O | — |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Propagation Delay (tpd) | — | 35 ns (max) |
| Frekuensi Bawah Maximum | — | [DATA_NEEDED: fmax for this speed grade] |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Maximum Supply Voltage | — | 5.25 V (per distributor listing) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Rentang Suhu Kerja | — | 0°C to 70°C (Commercial) |
| Temperature Grade | — | Commercial |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Status RoHS | — | Compliant (per Altera listing) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |