EP1810LC-20T vs EP1810GM883 Perbandingan

Perbandingan bersamaan detil EP1810LC-20T dari Intel dan EP1810GM883 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1810LC-20T EP1810GM883
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Altera Classic EPLD Classic EPLD (EP1810 series)
Product Type CPLD (Complex Programmable Logic Device) —
Usable Gates 900 gates —
Macrocells 48 48
Logic Array Blocks (LABs) 4 x 12 macrocells —
Maximum Toggle Frequency 50 MHz —
Pin-to-Pin Logic Delay (tPD) 20 ns —
Supply Voltage (VCC) 5 V —
Package Type PLCC-68 (J-lead) —
Tipe Mounting Surface Mount (socket-compatible) Through-Hole (PGA socket)
Configuration Memory On-chip EEPROM (non-volatile) —
Programming Interface JTAG (IEEE 1149.1) and Altera Master/Slave serial —
Suhu Kerja 0C to +70C (commercial) -55C to +125C (MIL-STD-883 Class B)
Shipping Format Tape & Reel ("T" suffix) —
Status RoHS Non-compliant (legacy 5V PLCC) [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Device Type — UV-Erasable Programmable Logic Device (EPLD)
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Supply Voltage (Vcc) — 4.5 V to 5.5 V (nominal 5 V)
Propagation Delay (tpd) — 45 ns (max)
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
Process Technology — CMOS, UV-erasable
Paket — 68-Pin Ceramic Pin Grid Array (PGA)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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