EP1SGX25DF67216 vs EP1SGX25DF672I7N Perbandingan

Perbandingan bersamaan detil EP1SGX25DF67216 dari Altera dan EP1SGX25DF672I7N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1SGX25DF67216 EP1SGX25DF672I7N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family Stratix GX Stratix GX
Logic Elements 25,660 25,660
Total RAM Bits 1,944,576 —
Embedded Multipliers (18x18) [DATA_NEEDED: 18x18 multiplier count] —
Number of PLLs 4 —
Number of Transceiver Channels 8 (4 in each of 2 banks) —
Max Transceiver Data Rate 3.1875 Gbps per channel —
Min Transceiver Data Rate 500 Mbps —
Core Supply Voltage 1.5 V —
Auxiliary Supply Voltage 3.3 V —
I/O Supply Voltage 1.5 V / 1.8 V / 2.5 V / 3.3 V (per bank) —
Maximum User I/O Pins [DATA_NEEDED: user I/O count for DF672 package] —
Paket 672-ball FineLine BGA (DF672) 672-ball FineLine BGA (FC-FBGA), 33 × 33 mm, 1 mm pitch
Tipe Mounting Surface Mount (BGA) Surface Mount (BGA)
Suhu Kerja Industrial, -40C to +100C (I-suffix family) 0 °C to 85 °C (industrial)
On-Die Termination Yes, 100-ohm differential —
Pre-emphasis / Equalization Programmable (transmitter pre-emphasis; receiver adaptive equalization) —
Configuration Schemes Passive serial, fast passive parallel, JTAG, Altera enhanced configuration —
Status RoHS Lead-free / RoHS compliant (per Altera product family documentation) [DATA_NEEDED: rohs status]
CLBs — 2,566
Maximum Operating Frequency — 4385.97 MHz (logic); 4.7 MHz (combinatorial CLB delay rating)
Combinatorial Delay (CLB) — 9.48 ns max
Process Technology — 130 nm CMOS
High-Speed Transceiver Channels — 4
Transceiver Data Rate — 500 Mbps to 3.1875 Gbps per channel
Core Supply Voltage (VCCINT) — 1.5 V
Supply Voltage Range — 1.425 V to 1.575 V
Logic Family — CMOS
Lead-Free — Yes
Terminal Form — Ball (BGA)
Number of Terminals — 672

Spek dan Sumber

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