EP1SGX25FF1020C6 vs EP1SGX25FF1020 Perbandingan
Perbandingan bersamaan detil EP1SGX25FF1020C6 dari Intel dan EP1SGX25FF1020 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EP1SGX25FF1020C6 - Stratix GX FPGA 25,660 LE 607 I/O FBGA-1020 | Intel
EP1SGX25FF1020C6 ObsoletePerbandingan Spesifikasi
| Parameter Umum | EP1SGX25FF1020C6 | EP1SGX25FF1020 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Series | Stratix GX | — |
| Logic Family | CMOS | — |
| Logic Elements / Cells | 25,660 | — |
| Number of LABs | 2,566 | — |
| Total Memory Bits | 1,944,576 (1.94 Mbit, TriMatrix) | — |
| User I/O Count | 607 | — |
| Jumlah Pin | 1020 | — |
| Package Type | FBGA-1020 (FC-FBGA) | — |
| Package Dimensions | 33 x 33 mm | — |
| Ball Pitch | 1.0 mm | — |
| Core Supply Voltage | 1.5 V | — |
| Suhu Kerja | 0 °C to 85 °C (Commercial) | -40C to +85C (industrial variant) / 0C to +85C (commercial variant) |
| Speed Grade | C6 | — |
| Tipe Mounting | Surface Mount | Surface Mount (BGA) |
| Status RoHS | Non-Compliant (legacy Altera era) | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | Yes | — |
| Logic Elements (LE) | — | 25,660 |
| Configurable Logic Blocks (CLB) | — | 2,566 |
| Embedded Memory (bits) | — | 1,944,576 |
| Process Technology | — | 130 nm CMOS |
| Logic Cells (per FPGAkey) | — | 25,660 |
| Combinatorial Delay (Tpd) | — | 7.49 ns (per Microchip USA datasheet summary) |
| Operating Frequency (max) | — | [DATA_NEEDED: max internal operating frequency] |
| Paket | — | 1020-ball FCBGA (PBGA, 1.00 mm pitch) |
| Pin/Package Count | — | 1020 |
| Tegangan Pemuat | — | [DATA_NEEDED: core VCC voltage] |
| Serial Transceivers | — | Embedded SERDES (multi-gigabit, protocol-dependent) |
| DSP Blocks | — | Embedded dedicated multipliers |
| PLL / Clock Management | — | Embedded PLLs |
| Configuration Method | — | SRAM-based, configuration via JTAG / passive serial / fast passive parallel |