EP1SGX40F1020C5N vs EP1SGX40FF1020C7 Perbandingan
Perbandingan bersamaan detil EP1SGX40F1020C5N dari Intel dan EP1SGX40FF1020C7 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP1SGX40F1020C5N | EP1SGX40FF1020C7 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Family | Stratix GX | Stratix GX (EP1SGX40) |
| Logic Elements | 41,250 | — |
| Total Memory Bits | 3,423,744 | — |
| User I/O Count | 624 | — |
| Paket | 1020-BBGA (FCBGA) | 1020-ball FC-FBGA (S-PBGA-B1020) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Speed Grade | C5 (commercial) | 7 (-7, mid-speed) |
| Suhu Kerja | 0C to +85C (commercial) | 0 °C to 85 °C (commercial) |
| Core Voltage | 1.5 V | — |
| Number of Transceivers | [DATA_NEEDED: number of transceiver channels] | — |
| Max Transceiver Data Rate | [DATA_NEEDED: max transceiver data rate Gbps] | — |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Yes (N suffix) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Configuration Method | JTAG / Passive Serial | — |
| Series | — | Stratix GX |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Process Technology | — | CMOS |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| PLLs | — | 8 enhanced + per-transceiver PLLs |