EP1SGX40FF1020C6 vs EP1SGX40FF1020C7 Perbandingan
Perbandingan bersamaan detil EP1SGX40FF1020C6 dari Altera dan EP1SGX40FF1020C7 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP1SGX40FF1020C7 - Stratix GX FPGA 41,250 LE | Intel | 1020-BGA
EP1SGX40FF1020C7 ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP1SGX40FF1020C6 | EP1SGX40FF1020C7 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Family | Stratix GX | Stratix GX (EP1SGX40) |
| Series | EP1SGX40 | Stratix GX |
| Logic Elements (LEs) | 41,250 | — |
| Configurable Logic Blocks (CLBs) | 4,125 | — |
| Embedded Memory | 3,423,744 bits | — |
| Logic Family | CMOS, SRAM-based LUT | — |
| Core Supply Voltage | 1.5 V | — |
| Speed Grade | C6 | 7 (-7, mid-speed) |
| Suhu Kerja | 0 C to 85 C (Commercial) | 0 °C to 85 °C (commercial) |
| Paket | 1020-ball FBGA (PBGA), 1.00 mm pitch, 33 x 33 mm | 1020-ball FC-FBGA (S-PBGA-B1020) |
| Tipe Mounting | Surface Mount | Surface Mount |
| High-Speed Transceivers | Up to 20 channels (Stratix GX) | — |
| Configuration Method | SRAM-based, external configuration device required | — |
| Status RoHS | Compliant | Compliant |
| Level MSL | [DATA_NEEDED: MSL Level] | — |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Process Technology | — | CMOS |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| Transceiver Channels | — | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| PLLs | — | 8 enhanced + per-transceiver PLLs |