EP20K200CF484I7 vs EP20K200CF484C9N Perbandingan
Perbandingan bersamaan detil EP20K200CF484I7 dari Altera dan EP20K200CF484C9N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EP20K200CF484I7 - APEX 20KC 200K Gates FPGA 1.8V FBGA-484 | Altera
EP20K200CF484I7 ⚠ Waktu Beli Terakhir
Perbandingan Spesifikasi
| Parameter Umum | EP20K200CF484I7 | EP20K200CF484C9N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 8,320 | 8,320 |
| Typical Gate Count | 200,000 system gates | — |
| Maximum Operating Frequency | 375.94 MHz (per device-family data) | — |
| Process Technology | 0.15 µm CMOS with copper interconnect | 0.15 um CMOS |
| Internal Supply Voltage (VCCINT) | 1.8 V (1.71 V to 1.89 V) | — |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | 3.3 V / 2.5 V / 1.8 V / 1.5 V (MultiVolt) |
| User I/O Pins | 376 | — |
| Dedicated Inputs | 4 | — |
| Paket | 484-pin FBGA (FineLine BGA) | 484-pin FineLine BGA (FBGA) |
| Package Body Size | 23 mm × 23 mm | — |
| Ball Pitch | 1.000 mm | — |
| Speed Grade | -7 | C9 (250 MHz) |
| Temperature Grade (I7 suffix) | Industrial, -40 °C to +85 °C | — |
| Configuration Technology | SRAM-based, re-programmable in-system | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Propagation Delay | [DATA_NEEDED: datasheet-specified tpd] | — |
| Device Type | — | FPGA (Field-Programmable Gate Array) |
| Typical Gates | — | 200,000 |
| Embedded System Block (ESB) Bits | — | 106,496 |
| Maximum User I/O | — | 376 |
| Frekuensi Bawah Maximum | — | 250 MHz |
| Core Supply Voltage (VCCINT) | — | 1.8 V |
| Temperature Grade | — | Industrial (0C to +85C) |
| Tipe Mounting | — | Surface Mount (BGA) |
| Configuration Scheme | — | SRAM-based, supports passive serial/parallel and JTAG |
| Level MSL | — | 3 (per JEDEC J-STD-020) |