EP20K600CB652C7ES vs EP20K600CB652C7 Perbandingan
Perbandingan bersamaan detil EP20K600CB652C7ES dari Altera dan EP20K600CB652C7 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP20K600CB652C7ES | EP20K600CB652C7 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 |
| System Gates | 600,000 | 600,000 |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | — |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm CMOS (all-layer copper interconnect) |
| Suhu Kerja | 0 °C to +85 °C (commercial) | Commercial (0C to +70C) |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| PLLs | 4 | — |
| Tipe Mounting | Surface Mount (BGA) | — |
| Series | — | APEX 20K |
| Embedded RAM | — | 311,296 bits |
| User I/O Count | — | 488 |
| Paket | — | 652-ball BGA |
| Core Voltage | — | 1.8 V |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Maximum Frequency | — | 375.94 MHz |
| Architecture | — | MultiCore (LUT + embedded memory) |
| Speed Grade | — | C7 |