EP20K600CB652C7ES vs EP20K600CB652C8N Perbandingan
Perbandingan bersamaan detil EP20K600CB652C7ES dari Altera dan EP20K600CB652C8N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP20K600CB652C7ES | EP20K600CB652C8N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 | 24,320 cells |
| System Gates | 600,000 | 600,000 |
| Maximum System Gates | 1,053,840 | — |
| Embedded Memory Bits | 311,296 | — |
| Embedded System Blocks (ESB) | 26 | — |
| Maximum User I/O | 488 | — |
| User I/O (this package) | 488 (652-BGA) | — |
| Supply Voltage - Core | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Maximum Internal Clock Frequency | 1666.6 MHz | — |
| Propagation Delay | 1.6 ns | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm all-layer copper-metal |
| Suhu Kerja | 0 °C to +85 °C (commercial) | 0 °C to 85 °C (commercial) |
| Package Type | 652-ball FineLine BGA | — |
| JEDEC Package Code | S-PBGA-B652 | — |
| Configuration Modes | Passive Serial, Passive Parallel, JTAG | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | unknown |
| PLLs | 4 | — |
| Tipe Mounting | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | Loadable PLD / FPGA |
| Embedded Memory | — | 311,296 bits |
| User I/O Pins | — | 488 |
| Dedicated Inputs | — | 4 |
| Outputs | — | 480 |
| Propagation Delay (typ.) | — | 1.48 ns |
| Pin-to-Pin Timing | — | 1.78 ns |
| Internal Frequency (typ.) | — | 301.21 MHz |
| Core Supply Voltage | — | 1.8 V nominal (1.71 V to 1.89 V) |
| Speed Grade | — | C8 |
| Paket | — | 652-ball LBGA, 45 x 45 mm, 1.27 mm pitch |
| Architecture | — | MultiCore LUT + Embedded System Blocks (ESB) |
| Pin-Compatible With | — | APEX 20KE family |