EP2S60F1020C5N vs EP2S60F1020C4N Perbandingan

Perbandingan bersamaan detil EP2S60F1020C5N dari Altera dan EP2S60F1020C4N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EP2S60F1020C5N EP2S60F1020C5N - Stratix II FPGA 60K LE | Altera

EP2S60F1020C5N - Stratix II FPGA 60K LE | Altera

EP2S60F1020C5N ✓ Aktif

Perbandingan Spesifikasi

Parameter Umum EP2S60F1020C5N EP2S60F1020C4N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Obsolete
Series Stratix II Stratix II
Number of Logic Elements 60440 —
Number of LABs/CLBs 3022 —
Number of Logic Array Blocks 3022 LABs —
Total RAM Bits 2544192 bits —
Number of User I/O 718 —
Paket / Case 1020-BBGA, FCBGA —
Number of Terminals 1020 —
Terminal Form BALL —
Package Code BGA —
Package Shape SQUARE —
Tegangan Pemuat 1.15 V to 1.25 V —
Suhu Kerja 0°C ~ 85°C (TJ) —
Tipe Mounting Surface Mount Surface Mount (BGA)
Speed Grade / Order Code C5 (commercial speed grade per Altera order code) —
Status RoHS [DATA_NEEDED: RoHS status] EU RoHS compliant with exemption (per Arrow listing)
Moisture Sensitivity Level [DATA_NEEDED: MSL] —
Number of DSP Blocks [DATA_NEEDED: Number of DSP blocks] —
Number of M512 RAM Blocks [DATA_NEEDED: Number of M512 RAM blocks] —
Number of M4K RAM Blocks [DATA_NEEDED: Number of M4K RAM blocks] —
Family — Stratix II (EP2S60)
Logic Elements — 60,440
Adaptive Logic Modules (ALMs) — 30,220 (approx.)
Logic Array Blocks (LABs) — 3,022
Embedded Memory (bits) — 2,544,192
Embedded Memory Blocks — M512/M4K/M-RAM TriMatrix memory
DSP Blocks (18-bit x 18-bit) — Up to 48 (24 per DSP block column pair typical)
User I/Os — 718
Maximum Core Frequency — 711.24 MHz (per Arrow listing)
Core Voltage — 1.2 V
Process Technology — 90 nm CMOS
Paket — 1020-ball FC-FBGA (Fine-pitch Chip-Scale BGA)
Operating Temperature Grade — Commercial (C4 suffix indicates commercial, speed grade 4)
Configuration Modes — Passive Serial, Fast Passive Parallel, JTAG
PLLs / Clock Networks — Yes - on-chip PLLs and global clock networks

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