EP2SGX130GF40C4ES vs EP2SGX130GF40C4NES Perbandingan

Perbandingan bersamaan detil EP2SGX130GF40C4ES dari Intel dan EP2SGX130GF40C4NES dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP2SGX130GF40C4ES EP2SGX130GF40C4NES
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Unknown Waktu Pembelian Terakhir
Product Type Field-programmable gate array (FPGA) —
Product Family Stratix II GX —
Logic Cells 132,540 —
Configurable Logic Blocks 7,047 CLBs —
Logic Technology CMOS —
User I/O 734 I/O —
Internal Frequency 717 MHz —
Supply Voltage Range 1.15 V to 1.25 V —
Package Pin Count 1,508 pins —
Package Type FBGA-1508 —
Package Body Size 40 mm by 40 mm —
Ball Pitch 1 mm —
Package Designation MS-034AAU-1 —
Lead-Free Yes —
Tipe Mounting Surface mount Surface Mount (flip-chip BGA)
Rentang Suhu Kerja [DATA_NEEDED: operating temperature range] —
Transceiver Count [DATA_NEEDED: transceiver count] —
Configuration Memory Type [DATA_NEEDED: configuration memory type] —
Family — Stratix II GX
Logic Elements — 132,540
Logic Blocks / ALMs — Approximately 53,000 ALMs
Process Technology — 90 nm CMOS
Core Voltage — 1.2 V
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Speed Grade — C4 (speed grade -4)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
DSP Blocks — Yes (variable, see datasheet)
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
Level MSL — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
Suhu Kerja — Commercial Extended (per N suffix)
JEDEC Standard Reference — MS-034AAU-1

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