EP610PC25 vs EP610PC-20 Perbandingan
Perbandingan bersamaan detil EP610PC25 dari Altera dan EP610PC-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP610PC25 | EP610PC-20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Logic Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V ±10% |
| Programming Voltage (VPP) | 12 V | — |
| ICC (typical) | 200 mA | — |
| Suhu Kerja | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Paket | PDIP-24 | PDIP-24 |
| Tipe Mounting | Through-Hole | — |
| Programmability | One-Time-Programmable (OTP), UV-erasable variant exists | — |
| Jumlah Pin | 24 | — |
| Technology | 5 V CMOS | — |
| Status RoHS | unknown | Non-compliant (legacy PDIP) |
| Lifecycle | Obsolete (last shipped ~2000s) | — |
| Family | — | Classic EPLD |
| Logic Elements | — | 16 macrocells |
| Maximum Operating Frequency | — | 100 MHz (pipelined) |
| Jumlah Pin | — | 24 |
| Process Technology | — | CMOS EPROM |
| Programmable Flip-Flops | — | 16 |
| Input Pins | — | 24 |
| Output Pins | — | 16 |
| I/O Compatibility | — | TTL |
| Program/Erase Method | — | UV (windowed) or OTP |