EP910PC-25 vs EP910PC-20 Perbandingan
Perbandingan bersamaan detil EP910PC-25 dari Altera dan EP910PC-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910PC-25 | EP910PC-20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Family | Classic EPLD | — |
| Usable Gates | 900 | 900 |
| Integration Gates (typical) | 4800 | — |
| Macrocells | 24 | — |
| Pin-to-Pin Delay (tPD) | 25 ns | 20 ns |
| Maximum Operating Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 5 V +/- 10% | 5 V |
| Technology | CMOS EPROM | CMOS EPROM (UV-erasable) |
| Paket | PDIP-24 (Plastic DIP) | PDIP-24 (PC suffix) |
| Jumlah Pin | 24 | 24 |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| TTL Compatibility | 100% TTL emulation | — |
| Suhu Kerja | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Erasure Method | Not erasable in plastic package (windowless) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Macrocell Count | — | [DATA_NEEDED: macrocell count] |
| I/O Compatibility | — | 100% TTL |
| Programming Method | — | EPROM programmer, JEDEC fuse map |
| Tipe Mounting | — | Through-Hole (DIP) |
| Level MSL | — | [DATA_NEEDED: MSL level] |
| Status RoHS | — | [DATA_NEEDED: RoHS status] |