EPC1064VLC20 vs EPC1441LI20 Perbandingan
Perbandingan bersamaan detil EPC1064VLC20 dari Altera dan EPC1441LI20 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC1064VLC20 | EPC1441LI20 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Tipe Memori | OTP (One-Time Programmable) Configuration PROM | OTP Configuration PROM (PROM) |
| Ukuran Memori | 65,536 bit (64 Kb) | — |
| Organisasi | 64K x 1 (serial) | — |
| Antarmuka | Serial, daisy-chain capable | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | — |
| Programmable Type | OTP (factory programmed; not in-system programmable) | — |
| Paket | 20-pin PLCC (J-lead, 9 x 9 mm) | 20-pin PLCC (J-lead, 9x9 mm) |
| Suhu Kerja | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Compatible FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Cascade Support | Yes, daisy-chain output for up to 8 devices | — |
| Tipe Mounting | Surface Mount (PLCC socket compatible) | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Level MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Programming Method | Altera programming hardware (factory, pre-solder) | One-Time-Programmable via Altera programming hardware |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Configuration Interface | — | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Tegangan Pemuat | — | 3.3 V |
| Pin Pitch | — | 1.27 mm |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |