EPC144PC8 vs EPC1L120 Perbandingan
Perbandingan bersamaan detil EPC144PC8 dari Intel dan EPC1L120 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EPC1L120 - Altera/Intel Configuration Device 120 kbit Serial | PLCC-20
EPC1L120 ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EPC144PC8 | EPC1L120 |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Manufacturer | Altera (now Intel) | — |
| Part Type | Serial Configuration PROM / Configuration Device | — |
| Internal Manufacturer Number | 433800612 | — |
| Memory Technology | EPROM (one-time programmable) | — |
| Paket / Case | DIP-8 (PDIP-8, through-hole) | — |
| Tegangan Pemuat | 4.75 V to 5.25 V | — |
| Suhu Kerja | 0 °C to +70 °C | -40C to +85C (industrial) |
| Antarmuka | Altera serial configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Compatible FPGA Series | Altera FLEX 8000, FLEX 10K, APEX 20K, EPF10K family | — |
| Programming Method | ByteBlaster / BitBlaster via Quartus or MAX+PLUS II | — |
| Configuration Mode | Passive Serial (PS) | — |
| Endurance | 100k write/erase cycles typical (EPROM) | — |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Tipe Mounting | Through-Hole (THT) | Surface Mount / Through-Hole (socket) |
| Tipe Memori | — | Configuration EEPROM |
| Memory Capacity | — | 120 kbit |
| Tipe Antarmuka | — | Serial (Altera configuration protocol) |
| Tegangan Pemuat Kerja | — | 3.3 V / 5 V |
| Output Compatibility | — | MultiVolt: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V |
| Programmability | — | In-System via JTAG (IEEE 1149.1) |
| JTAG Support | — | Yes (dedicated JTAG port) |
| Paket | — | PLCC-20 |
| Reprogram Cycles | — | 100 cycles typical |
| Compatible Altera FPGAs | — | FLEX 6000, FLEX 8000, MAX 7000, MAX 9000 families |
| Cascade Support | — | Yes (multi-FPGA configuration chains) |
| Level MSL | — | [DATA_NEEDED: MSL level] |