EPC2-TC32 vs EPC2TC32N Perbandingan
Perbandingan bersamaan detil EPC2-TC32 dari Intel dan EPC2TC32N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2-TC32 | EPC2TC32N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Tipe Memori | EPROM (OTP/UV-erasable configuration PROM) | Flash Configuration PROM |
| Ukuran Memori | 1.6 Mbit | 1.6 Mbit |
| Tipe Antarmuka | Serial | — |
| Organisasi | Serial bitstream output | — |
| Programmability | In-System Programmable (ISP) via JTAG (IEEE 1149.1) | — |
| Tegangan Pemuat | 3.3 V | — |
| Rentang Suhu Kerja | 0C to +70C (Commercial) | — |
| Paket | 32-pin TQFP (7x7 mm) | 32-TQFP (7x7 mm) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Supported FPGA Families | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Mode | Serial (FPP/MSD via FPGA master/slave) | Serial (AS) or Parallel (PS/AP) |
| Output Control | OE and nCS gating internal tri-state buffer | — |
| Internal Oscillator | Yes (drives address counter) | — |
| Level MSL | MSL 3 (168 hours) | — |
| Status RoHS | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| Programmable Type | — | In System Programmable (ISP) |
| Antarmuka | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Suhu Kerja | — | 0 °C to +70 °C (Commercial) |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |