EPC2LC20 vs EPC1L20 Perbandingan

Perbandingan bersamaan detil EPC2LC20 dari Altera dan EPC1L20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2LC20 EPC1L20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup NRND Aktif
Tipe Memori Non-volatile configuration PROM OTP Configuration PROM (Flash)
Ukuran Memori 1.6 Mbit 1 Mbit
Configuration Interface Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE —
Programming Interface IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant —
Supply Voltage VCC 3.0 V to 3.6 V (3.3-V operation) —
ISP Voltage Range 5.0 V or 3.3 V —
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 —
Cascade Support Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams —
Paket 20-pin PLCC (J-lead, 9x9 mm) 20-pin PLCC (9x9 mm)
Tipe Mounting Surface Mount Through-Hole / Socket
Suhu Kerja -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] [DATA_NEEDED: operating temperature range]
Status RoHS Non-Compliant (original Altera Pb-containing part) [DATA_NEEDED: RoHS compliance]
Lead-Free Version EPC2LC20N available as lead-free equivalent —
Programming Support Altera Programming Unit (APU), Quartus II, JTAG programmer —
Boundary-Scan IEEE 1149.1 compliant, 8-bit or 16-bit JTAG —
Configuration Clock (max) — 8 MHz
Flash Access Time — 90 ns (approx.)
Max Read Bandwidth — 160 Mbps (16-bit DQ bus)
Antarmuka — Serial / FPP configuration + JTAG (IEEE 1149.1)
Tegangan Pemuat — 3.3 V (typical)
Programmability — One-Time Programmable (OTP)
JTAG / ISP Support — Yes (IEEE 1149.1)
Compatible FPGA Series — Stratix, Cyclone, APEX, FLEX, ACEX, LUT-based families
Lead-Free — [DATA_NEEDED: lead-free status]

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