EPC2LC20 vs EPC2-TC32 Perbandingan
Perbandingan bersamaan detil EPC2LC20 dari Altera dan EPC2-TC32 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2LC20 | EPC2-TC32 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | NRND | Waktu Pembelian Terakhir |
| Tipe Memori | Non-volatile configuration PROM | EPROM (OTP/UV-erasable configuration PROM) |
| Ukuran Memori | 1.6 Mbit | 1.6 Mbit |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | Stratix I/II, Cyclone I/II, APEX 20K/II, Mercury, ACEX 1K, FLEX 10K |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| Paket | 20-pin PLCC (J-lead, 9x9 mm) | 32-pin TQFP (7x7 mm) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Suhu Kerja | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | — |
| Status RoHS | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS status - datasheet does not specify in retrieved snippet] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Tipe Antarmuka | — | Serial |
| Organisasi | — | Serial bitstream output |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Tegangan Pemuat | — | 3.3 V |
| Rentang Suhu Kerja | — | 0C to +70C (Commercial) |
| Configuration Mode | — | Serial (FPP/MSD via FPGA master/slave) |
| Output Control | — | OE and nCS gating internal tri-state buffer |
| Internal Oscillator | — | Yes (drives address counter) |
| Level MSL | — | MSL 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |