EPC2LI20N vs EPC2LC22N Perbandingan
Perbandingan bersamaan detil EPC2LI20N dari Altera dan EPC2LC22N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2LI20N | EPC2LC22N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Tipe Memori | Non-volatile configuration PROM (Flash) | Configuration PROM (non-volatile) |
| Ukuran Memori | 1.6 Mbit | 1.6 Mbit |
| Programmable Type | In System Programmable (ISP via JTAG) | — |
| Configuration Mode | Serial | — |
| Maximum Configuration Frequency | 10 MHz | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| Supply Voltage (VCCIO) | 4.5 V to 5.5 V | — |
| Paket / Case | 20-PLCC (J-Lead), 9x9 mm | — |
| Tipe Mounting | Surface Mount | Surface Mount / Through Hole socket |
| Packaging | Tube | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Supported FPGA Series | ACEX 1K, APEX II, Cyclone, Stratix II | — |
| JTAG Interface | IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO) | — |
| Configuration Pins | nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Tegangan Pemuat | — | 2.5 V (LC core) |
| Antarmuka | — | Serial configuration / JTAG (IEEE 1149.1) |
| Programmability | — | In-system programmable (ISP) via JTAG |
| Cascadable | — | Yes - supports multi-device configuration chains |
| Paket | — | PLCC-22 (Plastic Leaded Chip Carrier) |
| Configuration Compatibility | — | Altera APEX, ACEX, Mercury, Cyclone, Stratix series FPGAs |
| JTAG Pins | — | TCK, TMS, TDI, TDO |
| Internal Oscillator | — | Yes (built-in configuration timing) |
| Level MSL | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Status | — | Legacy / Obsolete (replaced by flash-based FPGA configuration) |