EPF10K130EBC356-1N vs EPF10K130EBC356-3 Perbandingan

Perbandingan bersamaan detil EPF10K130EBC356-1N dari Altera dan EPF10K130EBC356-3 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPF10K130EBC356-1N EPF10K130EBC356-3
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family FLEX 10KE FLEX-10KE
Typical Gates 130,000 130,000
Maximum System Gates [DATA_NEEDED: maximum system gates for EPF10K130E] —
Logic Elements (LEs) 6,656 —
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count for EPF10K130E] 12
Total RAM Bits 65,536 24,576 bits (12 EABs × 2 Kbit)
User I/O Pins 274 —
Paket 356-LBGA 356-LBGA (35x35 mm)
Package Code LBGA —
Logic Family CMOS CMOS
Process Technology 0.22 µm 0.22 µm SRAM-based CMOS
Core Supply Voltage 2.5 V 2.375 V to 2.625 V
I/O Supply Voltage 3.3 V 2.5 V / 3.3 V / 5.0 V (multiVolt I/O)
Speed Grade -1 -3 (fastest)
Propagation Delay 0.6 ns —
Maximum Internal Frequency 333.33 MHz —
Suhu Kerja 0 °C to 70 °C (Commercial) 0 °C to +70 °C (Commercial)
JTAG Boundary-Scan IEEE Std. 1149.1-1990 compliant —
PCI Compliance PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V) —
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N] Non-compliant (SnPb ball finish on legacy BGA)
Series — FLEX-10KE
Logic Elements — 8,192
Logic Array Blocks (LABs) — 832
Maximum User I/Os — 274
Pin-to-Pin Propagation Delay (-3 grade) — 0.6 ns
Configuration Method — SRAM-based, JTAG (IEEE 1149.1) in-system programmable
Lead-Free — No
Lifecycle — Obsolete — last-time-buy / Rochester Electronics stock only

Spek dan Sumber

Buka Semua Produk Buat BOM Ajukan Diskon