EPM3032ALC44-10N vs EPM3032ALC44-4 Perbandingan

Perbandingan bersamaan detil EPM3032ALC44-10N dari Altera dan EPM3032ALC44-4 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3032ALC44-10N EPM3032ALC44-4
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Logic Gates 600 gates —
Macrocells 32 32
Logic Array Blocks (LABs) 2 2
User I/O Pins 34 34
Propagation Delay (tPD) 10 ns —
Internal fMAX 103.1 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) —
Technology CMOS EEPROM-based CMOS EEPROM-based
In-System Programmability Yes, via IEEE 1149.1 JTAG —
ISP Standard Compliance IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes, IEEE 1149.1 compliant —
Paket 44-pin PLCC (J-Lead, surface mount) 44-pin PLCC (J-Lead)
Tipe Mounting Surface Mount Surface Mount (PLCC J-Lead)
Suhu Kerja [DATA_NEEDED: industrial/commercial range] 0°C to +70°C (Commercial)
Status RoHS [DATA_NEEDED: compliant or non-compliant] [DATA_NEEDED: RoHS status]
Pin-to-Pin Delay (tPD) — 4.5 ns
Maximum Counter Frequency — 227.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible)
Usable Gates — 600 to 10,000 (MAX 3000A family range)
In-System Programmability (ISP) — Yes, IEEE Std. 1532 compliant
Boundary-Scan Test — IEEE Std. 1149.1 (JTAG)
Programming Interface — JTAG (ByteBlaster / MasterBlaster)

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