EPM3256AQC208-10N vs EPM3256AQC208-7N Perbandingan

Perbandingan bersamaan detil EPM3256AQC208-10N dari Altera dan EPM3256AQC208-7N dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3256AQC208-10N EPM3256AQC208-7N
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Aktif
Series MAX 3000A —
Programmable Type In-System Programmable (EEPROM) —
Number of Macrocells 256 —
Number of Logic Elements/Blocks 16 LABs —
Usable Gates 10,000 —
Number of I/O Pins 161 (158 user I/O per Arrow listing) —
Propagation Delay (tpd) 10 ns (max) —
Maximum Counter Frequency 227.3 MHz —
Supply Voltage - Internal 3.0 V to 3.6 V (3.3 V typical) —
Suhu Kerja 0C to +70C (Commercial) 0 C to +70 C (Commercial)
Paket / Case 208-BFQFP / 208-PQFP (28x28 mm) —
Tipe Mounting Surface Mount Surface Mount
ISP Compliance IEEE Std. 1532 —
Boundary Scan IEEE Std. 1149.1 (JTAG) —
I/O Tolerance 5 V tolerant, MultiVolt interface —
Status RoHS [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] [DATA_NEEDED: RoHS status]
Family — MAX 3000A
Device Type — CPLD - Complex Programmable Logic Device
Macro Cells — 256
User I/Os — 161
Logic Gates (Usable) — 5,000
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency — 126.6 MHz
Supply Voltage VCCINT — 3.3 V
I/O Supply Voltage VCCIO — 3.3 V or 2.5 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programmability — Yes, IEEE Std. 1532 compliant
JTAG Boundary Scan — Yes
Paket — 208-pin PQFP

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