EPM3256ATC144-10N vs EPM3256ATC144-7N Perbandingan
Perbandingan bersamaan detil EPM3256ATC144-10N dari Altera dan EPM3256ATC144-7N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Waktu Beli TerakhirAltera
EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera
EPM3256ATC144-7N ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EPM3256ATC144-10N | EPM3256ATC144-7N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Waktu Pembelian Terakhir |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 256 | 256 |
| Usable Gates | 5,000 (up to 10,000 usable in family) | — |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | IEEE 1149.1 boundary-scan |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Paket | 144-LQFP (TQFP, ATC suffix) | 144-pin TQFP |
| Tipe Mounting | Surface Mount | Surface Mount |
| Suhu Kerja | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | 0C to +70C (Commercial) |
| Status RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | Compliant |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Family | — | MAX 3000A |
| Logic Gates (usable) | — | 5,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| User I/Os | — | 116 |
| Maximum Internal Frequency | — | 126.6 MHz |
| Supply Voltage (VCCIO) | — | 3.0 V to 3.6 V |
| Programmable Logic Technology | — | CMOS EEPROM-based |
| In-System Programmable (ISP) | — | Yes (3.3 V) |
| Logic Family | — | CMOS |